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ACCES I/O Products, Inc. 

MADE IN THE USA 

mPCIe-AIO16-16F Family Manual 

 

Rev 01 

 

enEXT: 

SET enEXT to enable the “External IRQ” Digital Input Secondary Function on 

DIO 13 so the selected edge on the input will (optionally) generate IRQs. 

enSTART: 

SET enSTART to enable the “ADC Start Conversion” Digital Input Secondary Function on DIO 14 so the selected edge will cause a

n ADC Start Event and 

optionally generate an IRQ. 

Each Digital Input Secondary function has a configurable active edge, rising or falling.  SET the corresponding edge

XXX 

bit to select rising edge, CLEAR the bit for falling edge. 

I/O Group1:0 

SET each bit to configure the digital I/O bit in the associated I/O Group for use as digital outputs. CLEAR a

 

bit to configure the I/O Group for use as inputs. 

 

(D0 is I/O Group 0 which controls the output vs input direction of DIO 0; D1 is I/O Group 1 which controls the direction of DIO1) 

 

In Windows

1

, please consult the various samples (C#, Delphi, and more) to explore how to program the device.  The AIOAIO Software Reference Manual.pdf provides reference material 

covering all AIOAIO Library APIs. A quick reference of the most-applicable functions is provided, below: 

Under certain circumstances the following information might prove useful: 

 

PCI Express Mini Card Plug-and-Play Data 

BAR[n]  Description 

1:0  DMA Registers 

3:2  I/O Registers 

 

A NOTE ABOUT PERFORMANCE 

The PCI Express bus and the PCI Express Mini Card standard are capable of very high bandwidth, but the latency per-transaction is roughly the same as all the other busses 

 

it hasn’t 

improved in decades.  This means you can expect to usually see a not-less-than 1MHz transaction rate. Typical rates exceed 3MHz [0.3µs]. 

Unfortunately, modern Operating Systems have introduced a new source of latency, the kernel / userland division. Application code runs in userland, which must transition to the kernel 
in order to perform any hardware operation.  This transition adds quite a lot of latency, which varies between different OSes, motherboards and revisions thereof, etcetera.  A Windows 
XP system can see an additional 7µs per transaction; a modern computer might see 3µs or less.  Any transaction from the kernel itself, however, avoids this additional overhead. 

Real-time operating systems will enable the highest transaction rates possible, all the way up to the hardware limits. 

The latest information can always be found on the product page on the website.  Here are some useful links: 

Links to useful downloads 
ACCES web site 

http://acces.io

 

Product web page 

acces.io/mPCIe-DIO-24S

 

This manual 

acces.io/MANUALS/mPCIe-DIO-24S.pdf

 

Install Package 

acces.io/files/packages/mPCIe-DIO-24S Install.exe

 

Linux / OSX 

github.com/accesio/AIOComedi

 

 

 

1

 

In Linux or OSX please refer to the documentation at 

github.com/accesio/apci

.

 

Summary of Contents for MPCIE-AIO16-16F Series

Page 1: ...www ACCES IO 10623 Roselle Street 800 326 1649 http acces io mPCIe AIO16 16F San Diego CA 92121 1506 USA sales accesio com MADE IN THE USA 16 ANALOG INPUT 4 ANALOG OUTPUT FOR MINI PCI EXPRESS HARDWARE MANUAL MODELS MPCIE AIO16 16F FAMILY ...

Page 2: ...ial Inputs 7 channel by channel programmable differential input ranges from 0 64V up to 24 576V Sustained sampling rates up to 1MHz 2Msps A D starts via software or periodic hardware timer Ease of use 16 bit 2MSPS complete data acquisition system High impedance 8 channel input 1 MΩ Four 16 bit analog outputs 5 per channel programmable ranges 0V to 5V 0V to 10V 2 5V 5V 10V Outputs Drive 10mA Guaran...

Page 3: ...5mm sizes Some computers may provide stand offs Please consult your computer manufacturer if it requires a different size The mPCIe standard like its PCI Mini Card predecessor was designed assuming use primarily in Laptop or Notebook and similar devices where physical dimension is often the paramount design constraint In Data Acquisition and Control applications low weight and vibration tolerance ...

Page 4: ...le in the FIFO 30 R ADC FIFO Data ADC FIFO 38 W R ADC Control ADAS3022 and ADC Control bits 44 W R DIO Data 2 bits of DIO Data 48 W R DIO Control Digital Secondary Function enable bits and direction control for each I O Group DIO 1 and DIO 0 68 R Revision FPGA code revision All these registers can be operated from any operating system using any programming language using either no driver at all ke...

Page 5: ... Write 32 bits only bit D31 through D24 D23 through D20 D19 through D16 D15 through D0 Name UNUSED C3 C2 C1 C0 A3 A2 A1 A0 16 bit DAC Counts 0 FFFF Please refer to the LTC1664 Data Sheet for details Consult the AIOAIO Software Reference or our sample programs source to avoid the hassle DAC_SetRange1 iBoard iChannel iRange DAC_OutputV iBoard iChannel double Voltage ADC Base Clock Offset C of 32 bit...

Page 6: ...ame UNUSED FAF FAF Write any 12 bit value 0 4095 to set the amount of entries in the ADC FIFO allowed to accumulate before a FIFO Almost Full IRQ is fired In Software ADC Start mode ADC Rate Divisor 10 cleared to zero the FIFO is 32 bits wide able to hold up to 4095 conversion results statuses In all other ADC Start Modes the ADC FIFO is 64 bits wide holds two ADC Conversions statuses per FIFO ent...

Page 7: ...ow to translate RAW format ADC data into Volts or skip the hassle and use our AIOAIO dll API Library ADC_GetImmediateV iBoard pVolts iChannel iRange ADC_GetImmediateScanV iBoard pVolts etc ADC Control Offset 38 of 32 bit Memory BAR 1 Read Write 32 bits only bit D31 through D19 D18 D17 D16 D15 D14 through D12 D11 D10 D9 through D7 D6 D5 D4 D3 D2 D1 D0 Name UNUSED RSV CONFIG GO RSV INx2 0 COM RSV Ga...

Page 8: ...ta BAR n Description 1 0 DMA Registers 3 2 I O Registers A NOTE ABOUT PERFORMANCE The PCI Express bus and the PCI Express Mini Card standard are capable of very high bandwidth but the latency per transaction is roughly the same as all the other busses it hasn t improved in decades This means you can expect to usually see a not less than 1MHz transaction rate Typical rates exceed 3MHz 0 3µs Unfortu...

Page 9: ...30mA from mPCIe Bus I O Interface Connectors On card Molex 501190 4017 40 pin latching Mating Molex 501189 4010 On cable Male D Sub Miniature 37 pin Mating Female D Sub Miniature 37 pin Model Options T Extended Temperature Operation 40 to 85 C I 4 20mA inputs PD Pseudo differential inputs Sxx Special configurations 10 50mA inputs input voltage dividers conformal coating etc CHAPTER 9 CERTIFICATION...

Page 10: ... give the unit model number serial number and a description of the failure symptom s We may suggest some simple tests to confirm the failure We will assign a Return Material Authorization RMA number which must appear on the outer label of the return package All units components should be properly packed for handling and returned with freight prepaid to the ACCES designated Service Center and will ...

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