SERIES IP400 INDUSTRIAL I/O PACK 40-CHANNEL DIGITAL INPUT MODULE
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The IP400 ID PROM contents are shown in Table 3.2. Note
that the base-address for the IP module ID space (see your carrier
board instructions) must be added to the addresses shown to
properly access the ID PROM. Execution of an ID PROM Read
operation requires 1 wait state.
IP400 PROGRAMMING CONSIDERATIONS
To make programming and communicating with the board
easier, Acromag provides you with the Industrial I/O Pack Software
Library diskette. The functions provided are written in the “C”
programming language and can be linked into your application.
Refer to the “README.TXT” file in the root directory and the
“INFO400.TXT” file in the “IP400” subdirectory on the diskette for
details.
The following sections give some pointers for programming
interrupts.
Programming Interrupts
Digital input channels can generate interrupts for the following
conditions (channels 0-11 only):
•
Any Change-of-State (COS) at selected channels.
•
Input level (polarity) match at selected input channels.
Interrupts generated by the IP400 use interrupt request line
INTREQ0* (Interrupt Request 0). The interrupt release mechanism
employed is the Release On Register Access (RORA) type. This
means that the interrupter will release the Industrial I/O Pack
interrupt request line (INTREQ0) after the interrupt has been cleared
by writing a “1” to the appropriate bit position in the input channel
Interrupt Status Register.
The Interrupt Vector Register contains a pointer to an interrupt
handling routine. The lower 4 bits of this 8-bit number contain the
channel number of the interrupting channel. The upper 4 bits of this
8-bit number contain a user-programmable pointer to complete the
vector. As such, the vector may point to any one of 12 possible
locations to access the interrupt handling routine. If each of these 8
locations contain the same address (the address of a single interrupt
handling routine), one interrupt handling routine may be used to
service all possible channel interrupts.
Interrupt service is prioritized with the higher numbered channel
having a higher priority over the lower numbered channels. Thus,
Channel 11 has the highest priority and channel 0 the lowest. As
such, if multiple channel interrupts become pending at the same
time, the pointer corresponding to the highest numbered channel will
be delivered first. After the highest numbered channel interrupt is
serviced and cleared, an additional interrupt will be generated for the
next highest priority (pending) interrupt.
When using interrupts, input channel bandwidth should be
limited to reduce the possiblity of missing channel interrupts. For a
given input channel, this could happen if multiple changes occur
before the channel’s interrupt is serviced. The response time of the
input channels should also be considered when figuring this
bandwidth. The total response time is the sum of the input buffer
response time, plus the interrupt logic circuit response time, and this
time must pass before another interrupt condition will be recognized.
The following programming examples assume that the IP400 is
installed onto an Acromag AVME9630/9660 carrier board (consult
your carrier board documentation for compatibility details).
Programming Example for AVME9630/9660 Carrier Boards:
1. Clear the Global Interrupt Enable Bit in the Carrier Board Status
Register by writing a “0” to bit 3.
2. Perform Specific IP Module Programming - see the Change-of-
State or Level Match programming examples that follow, as
required for your application.
3. Write to the carrier board Interrupt Level Register to program the
desired interrupt level per bits 2, 1, & 0.
4. Write “1” to the carrier board IP Interrupt Clear Register
corresponding to the desired IP interrupt request(s) being
configured.
5. Write “1” to the carrier board IP Interrupt Enable Register bits
corresponding to the IP interrupt request to be enabled.
6. Enable interrupts from the carrier board by writing a “1” to bit 3
(the Global Interrupt Enable Bit) of the Carrier Board Status
Register.
IP Programming Example for Change-of-State Interrupts:
1. Program the upper 4 bits of the odd-addressed byte of the
Interrupt Vector Register with the user specified portion of the
interrupt vector. These 4 bits combined with the lower 4 bits
(the interrupting channel number) form a pointer to one of 12
possible locations in memory that contain the address of the
interrupt handling routine for the interrupting channel.
2. Select Change-of-State interrupts for channels by writing a “1”
to each channel’s respective bit in the Interrupt Type Register
for channels that are to generate interrupts.
3. Enable individual input channel interrupts by writing a “1” to
each channel’s respective bit in the Interrupt Enable Register.
4. Clear pending interrupts by writing a “1” to each channel’s
respective bit in the Interrupt Status Register.
Change-of-State Interrupts may now be generated by the input
channels programmed above for any Change-Of-State
transition.
IP Programming Example for Level (Polarity) Match Interrupts:
1. Program the upper 4 bits of the odd-addressed byte of the
Interrupt Vector Register with the user specified portion of the
interrupt vector. These 4 bits combined with the lower 4 bits
(the interrupting channel number) form a pointer to one of 12
possible locations in memory that contain the address of the
interrupt handling routine for the interrupting channel.
2. Select Polarity interrupts for channels by writing a “0”
to each channel’s respective bit in the Interrupt Type Register
for channels that are to generate interrupts.
3. Select the desired polarity (High/Low) level for interrupts by
writing a “0” (Low) or “1” (High) level to each channel’s
respective bit in the Interrupt Polarity Register.
4. Enable individual input channel interrupts by writing a “1” to
each channel’s respective bit in the Interrupt Enable Register.
5. Clear pending interrupts by writing a “1” to each channel’s
respective bit in the Interrupt Status Register.
Interrupts can now be generated by matching the input level with
the selected polarity for programmed interrupt channels.
