Chapter 1: Nios II Hardware Development
1–5
Nios II System Development Flow
May 2011
Altera Corporation
Nios II Hardware Development Tutorial
Analyzing System Requirements
The development flow begins with predesign activity which includes an analysis of
the application requirements, such as the following questions:
■
What computational performance does the application require?
■
How much bandwidth or throughput does the application require?
■
What types of interfaces does the application require?
■
Does the application require multithreaded software?
Based on the answers to these questions, you can determine the concrete system
requirements, such as:
■
Which Nios II processor core to use: smaller or faster.
■
What components the design requires and how many of each kind.
■
Which real-time operating system (RTOS) to use, if any.
■
Where hardware acceleration logic can dramatically improve system performance.
For example:
■
Could adding a DMA component eliminate wasted processor cycles copying
data?
■
Could a custom instruction replace the critical loop of a DSP algorithm?
Analyzing these topics involve both the hardware and software teams.
Defining and Generating the System in Qsys
After analyzing the system hardware requirements, you use Qsys to specify the
Nios II processor core(s), memory, and other components your system requires. Qsys
automatically generates the interconnect logic to integrate the components in the
hardware system.
You can select from a list of standard processor cores and components provided with
the Nios II EDS. You can also add your own custom hardware to accelerate system
performance. You can add custom instruction logic to the Nios II core which
accelerates CPU performance, or you can add a custom component which offloads
tasks from the CPU. This tutorial covers adding standard processor and component
cores, and does not cover adding custom logic to the system.
The primary outputs of Qsys are the following file types:
■
Qsys Design File (
.qsys
)—Contains the hardware contents of the Qsys system.
■
SOPC Information File (
.sopcinfo
)—Contains a description of the contents of the
.qsys
file in Extensible Markup Language File (
.xml
) format. The Nios II EDS uses
the
.sopcinfo
file to create software for the target hardware.
■
Hardware description language (HDL) files—Are the hardware design files that
describe the Qsys system. The Quartus II software uses the HDL files to compile
the overall FPGA design into an SRAM Object File (.
sof
).
