Installation and set-up
4.4.7 Writing data to the CPLD from the FPGA
To write from the RC200 FPGA to the CPLD:
1. Set up the address and data bus if not already tristated.
2. Wait at least 10ns.
3. Set nCS low.
4. Wait at least 10ns.
5. Set nRDWR high and enable the data bus.
6. Wait at least 40ns.
7. Tristate
nRDWR.
8. Set nCS high.
9. Tristate the data bus.
4.4.8 Transferring data between the FPGA and host
The parallel port can read and write data to the RC200 FPGA by accessing CPLD address 0. The
process is controlled by the CPLD.
To write data from the host (via the parallel port) to the FPGA:
1. Set nRDWR low.
2. Set PnCS low.
3. Send the data.
4. Set PnCS high.
5. Set
nRDWR
high.
To read data from the FPGA and write it to the host via the parallel port:
1. Set
nRDWR
high.
2. Set PnCS low.
3. Read the data.
4. Set PnCS high.
5. Set nRDWR low.
4.4.9 Using the FPGA in parallel port control mode
When the CPLD control line P9 is set low the RC200 FPGA has direct control over the parallel port. The
nRDWR signal (CPLD control line P2) defines the direction of the databus.
4.5 Parallel port
The RC200/203 has an IEEE 1284-compatible parallel port. You can use the parallel port to:
•
program the FPGA
(see page 19)
•
program the SmartMedia card
(see page 23)
•
read data from and write data to the FPGA
(see page 21)
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