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DSP56000/DSP56001 USER’S MANUAL
MOTOROLA
Operation:
Assembler Syntax:
( . . . . . ), #xx
➞
D
( . . . . . ) #xx,D
where ( . . . . . ) refers to any arithmetic or logical instruction which allows parallel moves.
Description: Move the 8-bit immediate data value (#xx) into the destination operand D.
If the destination register D is A0, A1, A2, B0, B1, B2, R0–R7, or N0–N7, the 8-bit imme-
diate short operand is interpreted as an unsigned integer and is stored in the specified
destination register. That is, the 8-bit data is stored in the eight LS bits of the destination
operand, and the remaining bits of the destination operand D are zeroed.
If the destination register D is X0, X1, Y0, Y1, A, or B, the 8-bit immediate short operand
is interpreted as a signed fraction and is stored in the specified destination register.
That is, the 8-bit data is stored in the eight MS bits of the destination operand, and the
remaining bits of the destination operand D are zeroed.
If the arithmetic or logical opcode-operand portion of the instruction specifies a given
destination accumulator, that same accumulator or portion of that accumulator may not
be specified as a destination D in the parallel data bus move operation. Thus, if the
opcode-operand portion of the instruction specifies the 56-bit A accumulator as its desti-
nation, the parallel data bus move portion of the instruction may not specify A0, A1, A2,
or A as its destination D. Similarly, if the opcode-operand portion of the instruction speci-
fies the 56-bit B accumulator as its destination, the parallel data bus move portion of the
instruction may not specify B0, B1, B2, or B as its destination D. That is, duplicate des-
tinations are NOT allowed within the same instruction.
Note: This parallel data move is considered to be a move-type instruction. Due to pipe-
lining, if an address register (R or N) is changed using a move-type instruction, the new
contents of the destination address register will not be available for use during the follow-
ing instruction (i.e., there is a single instruction cycle pipeline delay).
Example:
:
ABS B #$18,R1
;take absolute value of B, #$18
➞
R1
:
I
Immediate Short Data Move
I
Before Execution
After Execution
R1
R1
$0000
$0018
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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