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MOTOROLA
DSP56000/DSP56001 USER’S MANUAL
A - 3
N0 address offset register and the M0 address modifier register during actual address
computation and address register update operations. This unique implementation is
extremely powerful and allows the user to easily address a wide variety of DSP-oriented
data structures. All address register indirect modes use at least one set of address regis-
ters (Rn, Nn, and Mn), and the XY memory reference uses two sets of address registers,
one for the X memory space and one for the Y memory space.
The special addressing modes include immediate and absolute addressing modes as
well as implied references to the program counter (PC), the system stack (SSH or SSL),
and program (P) memory.
Addressing modes may also be categorized by the ways in which they may be used.
Xn
Input Register X1 or X0 (24 Bits)
Yn
Input Register Y1 or Y0 (24 Bits)
An
Accumulator Registers A2, A1, A0 (A2 — 8 Bits, A1 and A0 — 24 Bits)
Bn
Accumulator Registers B2, B1, B0 (B2 — 8 Bits, B1 and B0 — 24 Bits)
X
Input Register X = X1: X0 (48 Bits)
Y
Input Register Y = Y1: Y0 (48 Bits)
A
Accumulator A = A2: A1: A0 (56 Bits)*
B
Accumulator B = B2: B1: B0 (56 BIts)*
AB
Accumulators A and B = A1: B1 (48 Bits)*
BA
Accumulators B and A = B1: A1 (48 Bits)*
A10
Accumulator A = A1: A0 (48 Bits)
B10
Accumulator B= B1:B0 (48 bits)
* NOTE: In data move operations, shifting and limiting are performed when this register is specified
as a source operand. When specified as a destination operand, sign extension and possibly
zeroing are performed.
Data ALU Registers Operands
Table A-1 Instruction Description Notation
Rn
Address Registers R0 - R7 (16 Bits)
Nn
Address Offset Registers N0 - N7 (16 Bits)
Mn
Address Modifier Registers M0 - M7 (16 Bits)
Address ALU Registers Operands
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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