NXP Semiconductors i.MX6QSabreSD User Manual Download

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During normal operation, the static configuration of the sja1105 needs to be changed by the driver. In turn, this requires a switch
reset, which temporarily disrupts Ethernet traffic and PTP synchronization. After a switch reset, the PTP synchronization offset
may jump to a higher momentary range of +/- 2 500 000 ns. The list of reset reasons in the sja1105 kernel driver is:

• Enabling or disabling VLAN filtering, via the "ip link" command.
• Enabling or disabling PTP timestamping.
• Configuring the ageing time (which is done automatically by the kernel STP state machine when STP is active).
• Configuring the Time-Aware Scheduler via the tc-taprio command.
• Configuring the L2 policers (for MTU or for policing).

8.2.3 Synchronized 802.1Qbv demo

The objectives of this demonstration are the following:

• Synchronize the SJA1105 PTP clock using IEEE 802.1AS.
• Run the SJA1105 Time-Aware Scheduler (802.1Qbv engine) based on the PTP clock.
• Create a small switched TSN network with a flow requiring deterministic latency. Prove the latency is not affected by interfering

traffic.

In the topology described earlier in this chapter, the boards which need to be synchronized by PTP are hosts 1, 2 and the LS1021A-
TSN board. Host 3 only generates iperf traffic, which is not time-sensitive.
The following commands are required to start PTP synchronization using the 802.1AS profile on host 1 and 2:

ptp4l -i eth0 -f /etc/ptp4l_cfg/gPTP.cfg -m
phc2sys -a -rr --transportSpecific 0x1 --step_threshold 0.0002 --first_step_threshold 0.0002

Different output is expected on the two hosts. One will become PTP grandmaster and show the following logs:

• ptp4l:

Apr 07 17:20:24 OpenIL ptp4l[3267]: [13.067] port 1: link up
Apr 07 17:20:24 OpenIL ptp4l[3267]: [13.104] port 1: FAULTY to LISTENING on INIT_COMPLETE
Apr 07 17:20:27 OpenIL ptp4l[3267]: [16.113] port 1: LISTENING to MASTER on
ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES
Apr 07 17:20:27 OpenIL ptp4l[3267]: [16.113] selected local clock 00049f.fffe.05de06 as best master
Apr 07 17:20:27 OpenIL ptp4l[3267]: [16.113] port 1: assuming the grand master role
Apr 07 17:20:27 OpenIL ptp4l[3267]: [16.692] port 1: new foreign master 001f7b.fffe.630248-1
Apr 07 17:20:27 OpenIL ptp4l[3267]: [16.692] selected best master clock 00049f.fffe.05f627
Apr 07 17:20:27 OpenIL ptp4l[3267]: [16.692] port 1: assuming the grand master role

• phc2sys:

Apr 07 17:21:24 OpenIL phc2sys[3268]: [73.382] eno0 sys offset        12 s2 freq   +2009 delay   1560
Apr 07 17:21:25 OpenIL phc2sys[3268]: [74.382] eno0 sys offset         2 s2 freq   +2003 delay   1560
Apr 07 17:21:26 OpenIL phc2sys[3268]: [75.382] eno0 sys offset       -18 s2 freq   +1983 delay   1600
Apr 07 17:21:27 OpenIL phc2sys[3268]: [76.383] eno0 sys offset        27 s2 freq   +2023 delay   1600
Apr 07 17:21:28 OpenIL phc2sys[3268]: [77.383] eno0 sys offset         7 s2 freq   +2011 delay   1600
Apr 07 17:21:29 OpenIL phc2sys[3268]: [78.383] eno0 sys offset       -18 s2 freq   +1988 delay   1560
Apr 07 17:21:30 OpenIL phc2sys[3268]: [79.383] eno0 sys offset        -8 s2 freq   +1993 delay   1560

While the other board will become a PTP slave, as seen by the following logs:

• ptp4l:

Apr 07 17:23:14 OpenIL ptp4l[3778]: [68484.668] rms 17 max 36 freq +1613 +/- 15 delay 737
+/- 0
Apr 07 17:23:15 OpenIL ptp4l[3778]: [68485.668] rms 8 max 15 freq +1622 +/- 11 delay 737

NXP Semiconductors

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Open Industrial User Guide, Rev. 1.8, 05/2020

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