Dual Issue - Some versions of the cores can issue two instructions and execute two instructions at a time. Other versions of
the core will only execute a single instruction at a time. There are limitations of the instructions that can execute
concurrently. Each core in an MCU could be defined as either dual- or single-issue variation for a particular MCU.
Lock-step Type - For safety applications, two cores execute instructions in parallel and compare the results to identify errors
in the processor core. To reduce current requirements of the two cores running in parallel, one of the cores can be delayed by
one clock. This spreads the peak current requirements of the core. Not all cores support the lock-step option. In the previous
MPC56xx Family, the cores implemented a true lock-step where the two lock-step cores execute completely in parallel, with
no delay.
General Purpose Registers - Although all of the e200zx cores are 32-bit Power Architecture cores, some versions of the
cores support 64-bit registers that can be used by the Signal Processing Engine (SPE) Auxiliary Processing Unit (APU). Not
all devices support the SPE APU.
Signal Processing Instruction support - There are several options for signal processing extensions to the core, either the
Lightweight Signal Processing Unit or the Signal Processing Extension. These are shown in the following table. Some cores
do not support any signal processing instructions.
Table 4. Signal Processing instruction options
Signal Processing Instructions
Version
Description
Lightweight Signal Processing Unit
(LSP)
1
The Lightweight Signal Processing Unit (LSP) supports a limited
number of basic math instructions to speed digital signal processing
algorithms.
Signal Processing Extension
(SPE)
1.1
The Signal Processing Engine (SPE) Auxiliary Processing Unit
supports a full range of instructions for digital signal processing
algorithms. There are currently two major versions of the SPE (1.1 and
2.1) that are supported on the MPC57xx devices.
2
No signal processing instructions
—
Some core variations do not include any type of signal processing
extensions.
Saturation Instruction Support - To better support AutoSAR math functions, saturated math instructions are supported on
some variations/versions of the cores. This allows optimization of some AutoSAR system calls to a single instruction.
Floating Point - Basic floating point instructions are supported on some variations of the cores. These can be defined as part
of the base Power Architecture core. Either scalar or vector floating point options are supported. Vector mode is implemented
in the SPE APU.
2.2 e200zx bus interface and memory options
The cores interface to the rest of the system through a bus interface. The majority of the e200zx cores support a dual bus
structure (Harvard architecture) with a separate instruction fetch bus and a load/store bus.
The following table shows the differences between the e200z cores in regards to the cache sizes, local memory sizes, and bus
interface and control.
Table 5. e200zx cores bus interface and memory options
Device
Revision
Instantiation
Core Name
MPU
e2eECC
XBAR Bus
DTCM
ITCM
D-cache
I-cache
e200z210 based cores
Table continues on the next page...
Differences between MPC57xx e200zx cores
Qorivva MPC57xx e200zx Core Differences, Rev 0, 10/2013
Freescale Semiconductor, Inc.
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