BDM-610000075
Rev B
Chapter 4: Using the cpuModule
85
Reset Status Register
The cpuModule has several different signals on board which can cause a system reset. If a reset occurs, the reset
status register can be used to see which reset or resets have been asserted on the cpuModule.
The user has the ability to see which resets have been asserted. Resets can also be cleared.
•
Examine Resets
: Reading from I/O port 0x987 will indicate if a reset has been asserted. If a 1 is read, the
corresponding reset has been asserted. If a 0 is read from the bit, the reset has not been asserted
•
Clear Reset
: Each reset can be cleared by writing a 1 to the selected bit of I/O port 0x987.
Utility Reset
1 = reset asserted
0 = no reset
System Power Good
1 = reset asserted
0 = no reset
Main +5V Input
1 = reset asserted
0 = no reset
Memory Power
1 = reset asserted
0 = no reset
CPU Core Power
1 = reset asserted
0 = no reset
SIO Power Good
1 = reset asserted
0 = no reset
Management Power
1 = reset asserted
0 = no reset
Standby Power
1 = reset asserted
0 = no reset
Table 60
Reset Status I/O Address 987h - Read Access
D7
D6
D5
D4
D3
D2
D1
D0
Utility Reset
1 = clear reset
System Power Good
1 = clear reset
Main +5V Input
1 = clear reset
Memory Power
1 = clear reset
CPU Core Power
1 = clear reset
SIO Power Good
1 = clear reset
Management Power
1 = clear reset
Standby Power
1 = clear reset
Table 61
Reset Status I/O Address 987h - Write Access
D7
D6
D5
D4
D3
D2
D1
D0
Summary of Contents for BDM-610000075
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