Si2401
Preliminary Rev. 0.9
19
not yet received any data from the host, it recognizes this
as an end-of-frame, raise CTS, calculates the final CRC
code, transmits the code, and begins transmitting stop
flags.
4. After transmitting the first stop flag, the Si2401 lowers CTS
indicating that it is ready to receive the next frame from the
host. At this point, the process repeats as in Step 1.
The method of receiving HDLC frames is as follows:
1. After the call is connected, the Si2401 searches for flag
data. Then, once the first non-flag word is detected, the
CRC is continuously computed, and the data is sent
across the UART (8-bit data or 9-bit data mode) to the host
after removing the HDLC zero-bit insertion. The DTE rate
of the host must be at least as high as that of data
transmission. HDLC mode only works with 8-bit data
words; the ninth bit is used only for escape on TXD and
end-of-frame received (EOFR) on RXD.
2. When the Si2401 detects the stop flag, it sends the last
data word in the frame as well as the two CRC bytes and
determine if the CRC checksum matches. Thus, the last
two bytes are not frame data but are the CRC bytes, which
can be discarded by the host. If the checksum matches,
the Si2401 echoes “G” (good). If the checksum does not
match, the Si2401 echoes “e” (error). Additionally, if the
Si2401 detects an abort (seven or more contiguous ones),
it echoes an “A”.
When the “G”, “e”, or “A” (referred to as a frame result
word) is sent, the Si2401 raises the EOFR (end of frame
receive) pin (see Figure 4B). The GPIO1 pin must be
configured as EOFR by setting SE4[3] (GPE) =
1
. In
addition to using the EOFR pin to indicate that the byte is a
frame result word, if in 9-bit data mode (set
S15[0] (NBE) =
1
), the ninth bit is raised if the byte is a
frame result word. To program this mode, set
S0C[3] (9BF) =
1
and SE0[3] (ND) =
1
.
3. When the next frame of data is detected, EOFR is lowered,
and the process repeats at Step 1.
To summarize, when receiving HDLC frames, the host
begins receiving data asynchronously from the Si2401.
When each byte is received, the host should check the
EOFR pin (or the ninth bit). If the EOFR pin (or the ninth
bit) is low, the data is valid frame data. If the EOFR pin
(or the ninth bit) is high, the data is a frame result word.
Figure 4. HDLC Timing
B. Frame Receive
A. Frame Transmit
TXD
RXD
Start
Stop
Start
Host begins frame N
Frame N
Start
Start
Stop
Host finished sending frame N
Host begins frame N + 1
CTS
Frame N + 1
CRC Byte 2
Stop
Stop
Start
Start
Stop
Receive Data
EOFR
(or bit 9)
Si2400 ready for byte 1 of frame N
Note: Figure not to scale.
(CTS used as normal flow control.)
Si2401 detects end of frame N.
Si2401 ready for byte 1
of frame N + 1.
CRC Byte 1
Frame Result Word
