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Spartan-3A DSP 3400A Edition User Guide

UG498 (v2.2) November 17, 2008

Chapter 1:

Introduction

R

3.

System ACE Controller

The Xilinx System ACE controller allows a type I CompactFlash card to program the 
FPGA through the JTAG port. The System ACE controller supports up to eight 
configuration images on a single CompactFlash card. The configuration address DIP 
switches (332 on the top of the board) allow you to select what configuration image to 
use.

System ACE error and status LEDs indicate the operational state of the System ACE 
controller:

The DS19 LED blinks green to indicate that no CompactFlash card is present.

The DS19 LED lights green to indicate an error during configuration.

The DS18 LED blinks green to indicate an ongoing configuration operation.

The DS18 LED lights green to indicate a successful download.

Every time that a CompactFlash card is inserted in the CompactFlash reader, a 
configuration operation is initiated. Pressing the System ACE reset button (S9) 
reprograms the FPGA.

The FPGA pins used for the USB interface are shared with the System ACE interface. 
See the FPGA pin assignments on Table 1.

Note

: Configuration with the System ACE controller is enabled with the configuration 

DIP switches.

The board also features a System ACE failsafe mode. Under this mode, if the System 
ACE controller detects a failed configuration attempt, it automatically restarts under a 
predefined configuration image. The failsafe mode is enabled by inserting two 
jumpers across JP7 and JP8 (horizontally or vertically).

Caution

:

 

Exercise caution when handling a CompactFlash card in the vicinity of the 

board, as contact between the card's metallic parts and board components could create 
short-circuits.

The System ACE MPU port is connected to the FPGA. This connection allows the 
FPGA to use the System ACE controller to reconfigure the system or access the 
CompactFlash card as a generic FAT file system. The data bus for the System ACE 
MPU port is shared with the USB controller.

4.

CompactFlash Reader

The CompactFlash reader is used as an interface point between the Spartan-3A DSP 
3400A Edition board and a CompactFlash card. The CompactFlash card used is 
generally a Lexar Media 512-MB module.

L18

DDR2_0_DQS3_P

H24

DDR2_LOOP_IN

Y22

DDR2_0_ODT_0

W20

DDR2_0_S0

U21

DDR2_0_ODT_1

V18

DDR2_0_S1

Y20

DDR2_0_RAS_B

T20

DDR2_0_WE_B

Y23

DDR2_0_CKE_0

Y25

DDR2_0_CKE_1

Table 1-28:

FPGA DDR2 Interface Pin Assignments  

(Cont’d)

FPGA Pin

Description

FPGA Pin

Description

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Summary of Contents for XtremeDSP Spartan-3A DSP 3400A...

Page 1: ...latform User Guide optional UG498 v2 2 November 17 2008 optional XtremeDSP Development Platform Spartan 3A DSP 3400A Edition User Guide UG498 v2 2 November 17 2008 Downloaded from Elcodis com electron...

Page 2: ...ice at any time Xilinx assumes no obligation to correct any errors contained in the Documentation or to advise you of any corrections or updates Xilinx expressly disclaims any liability in connection...

Page 3: ...DDR2 clock rate to 133 MHz Soft Touch connector not compliant with Agilent probes FMC connector is in violation of some rules of the standard 10 2007 1 2 Updated Table 20 Serial Port FPGA Pin Assignme...

Page 4: ...Spartan 3A DSP 3400A Edition User Guide www xilinx com UG498 v2 2 November 17 2008 Downloaded from Elcodis com electronic components distributor...

Page 5: ...Bottom 40 FMC Expansion Connectors 43 DDR2 Memory 43 DDR2 Memory Expansion 43 DDR2 Clock Signal 43 DDR2 Signaling 44 MIG Compatibility 44 I2C Bus Addressing 44 Chapter 2 Configuration Options JTAG Con...

Page 6: ...UG489 v2 2 November 17 2008 www xilinx com XtremeDSP Spartan 3A DSP User Guide Downloaded from Elcodis com electronic components distributor...

Page 7: ...Bottom View of Spartan 3A DSP 3400A Edition Board 40 Chapter 2 Configuration Options Figure 2 1 Spartan 3A DSP 3400A Edition Board JTAG Chain 47 Chapter 3 Programming the IDT Clock Chip Figure 3 1 P2...

Page 8: ...XtremeDSP Spartan 3A DSP User Guide www xilinx com UG489 v2 2 November 17 2008 Downloaded from Elcodis com electronic components distributor...

Page 9: ...FMC 2 Expansion Connector Pin Assignments 2 31 Table 1 13 Reset Connection Pin Assignment 32 Table 1 14 Clock Generator Default Settings 33 Table 1 15 I2C FPGA Pin Assignments 33 Table 1 16 FPGA Fan C...

Page 10: ...XtremeDSP Spartan 3A DSP User Guide www xilinx com UG489 v2 2 November 17 2008 Downloaded from Elcodis com electronic components distributor...

Page 11: ...purpose of the User Guide and the conventions used in this document Chapter 1 Introduction identifies the major components parts and functionality of the Spartan 3A DSP 3400A Edition board Chapter 2 C...

Page 12: ...ore information Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol the two nets are not connected Square brackets An optional entry or parameter However in bus specifications...

Page 13: ...Cross reference link to a location in another document See Figure 2 5 in the Virtex II Platform FPGA User Guide Blue underlined text Hyperlink to a website URL Go to http www xilinx com for the latest...

Page 14: ...14 www xilinx com Spartan 3A DSP 3400A Edition User Guide UG498 v2 2 November 17 2008 Preface About This Guide R Downloaded from Elcodis com electronic components distributor...

Page 15: ...DSP 3400A Edition Board Block Diagram DVI RJ45 10Base T 100Base TX 1000Base T Ethernet PHY CompactFlash CPLD SPI EEPROM ZBT SRAM 256 Mb FMC 34 diff 68 se 36 FMC 34 diff 68 se USB Peripheral USB Contro...

Page 16: ...strates the parts on the top of the Spartan 3A DSP 3400A Edition board Each numbered item in the diagram is followed by a numbered description X Ref Target Figure 1 2 Figure 1 2 Top View of Spartan 3A...

Page 17: ...in the I2C EEPROM The FPGA pins used for the USB interface are shared with the System ACE interface as identified in Table 1 1 2 USB Peripheral Port Type B connector used to connect peripheral USB dev...

Page 18: ...r device drives the digital and analog signals to the DVI connector 5 DVI Connector The display controller device is controlled through the I2C bus The DVI connector supports the I2C protocol allowing...

Page 19: ...e pins 2 3 or GMII mode pins 1 2 Table 1 4 defines the default configuration of the Ethernet PHY which can be modified through software Table 1 5 identifies the FPGA pin assignments for building new F...

Page 20: ...t how to configure the adjustable power supply The Flash memory shares the same address data bus as the ZBT synchronous SRAM 12 ZBT Synchronous SRAM 11 PS 2 Connectors The Spartan 3A DSP 3400A Edition...

Page 21: ...AM Make sure that FMC 1 adjustable power supply is configured for 3 3V to use the memory See 14 FMC Expansion Connector 1 for information about configuring the adjustable power supply 13 Soft Touch Co...

Page 22: ...V5 FMC_LA31_N A27 NC GND B1 NC GND B2 M8 FMC_LA08_P B3 M7 FMC_LA08_N B4 NC GND B5 K3 FMC_LA18_P B6 K2 FMC_LA18_N B7 NC GND B8 K5 FMC_LA10_P B9 K4 FMC_LA10_N B10 NC GND B11 P4 FMC_LA00_P_CC B12 P3 FMC...

Page 23: ...de the appropriate voltage to the FPGA bank used to communicate with the FMC module Be sure that the FMC adjustable power supply is configured for the voltage specified by the FMC module See FMC expan...

Page 24: ...C26 T5 0_LA27_P D26 N1 0_LA26_P C27 U4 0_LA27_N D27 N2 0_LA26_N C28 NC GND D28 NC GND C29 NC GND D29 A25 TCK C30 AF23 1 SCL D30 E23 TDI C31 AE25 1 SDA D31 NC TDO C32 NC GND D32 NC 3P3VAUX C33 NC GND D...

Page 25: ..._P G11 NC GND H11 B1 0_LA04_N G12 M8 0_LA08_P H12 NC GND G13 M7 0_LA08_N H13 E1 0_LA07_P G14 NC GND H14 F2 0_LA07_N G15 J7 0_LA12_P H15 NC GND G16 H6 0_LA12_N H16 J8 0_LA11_P G17 NC GND H17 J9 0_LA11_...

Page 26: ...FPGA and are used for the VCCIO of the FPGA banks connected to the FMC expansion connectors When no FMC expansion module is present the output voltage of PS1 should be set to 3 3V with the I2C bus int...

Page 27: ...rs for instructions about how to properly configure the adjustable power supplies X Ref Target Figure 1 3 Figure 1 3 Spartan 3A DSP 3400A Edition Board Power Supply LTM4601 12 A switching regulator LT...

Page 28: ...N D11 C21 1_LA05_P C12 NC GND D12 B21 1_LA05_N C13 NC GND D13 NC GND C14 D17 1_LA10_P D14 B7 1_LA09_P C15 C16 1_LA10_N D15 C7 1_LA09_N C16 NC GND D16 NC GND C17 NC GND D17 E14 1_LA13_P C18 C5 1_LA14_P...

Page 29: ...GND H5 C13 1_CLK0_M2C_N G6 B14 1_LA00_P_CC H6 NC GND G7 A14 1_LA00_N_CC H7 D23 1_LA02_P G8 NC GND H8 C23 1_LA02_N G9 B23 1_LA03_P H9 NC GND G10 A22 1_LA03_N H10 D20 1_LA04_P G11 NC GND H11 C20 1_LA04...

Page 30: ..._LA21_P G26 NC GND H26 C15 1_LA21_N G27 A8 1_LA25_P H27 NC GND G28 B8 1_LA25_N H28 H17 1_LA24_P G29 NC GND H29 G17 1_LA24_N G30 J12 1_LA29_P H30 NC GND G31 K12 1_LA29_N H31 J16 1_LA28_P G32 NC GND H32...

Page 31: ...FPGA 22 I2C Fan Controller and Temperature voltage Monitor Onboard temperature and voltage monitoring and control are handled by an Analog Devices ADT7476A device This device is controlled through I2C...

Page 32: ...The board supports configuration in several modes JTAG master serial slave serial master SelectMAP slave SelectMAP byte wide peripheral interface BPI up BPI down and SPI modes See Chapter 2 Configurat...

Page 33: ...low Turning the potentiometer located below the LCD with a screwdriver allows you to adjust the image contrast of the LCD The LCD is equipped with a backlight that can be turned off by removing jumper...

Page 34: ...21 defines how to use the configuration jumpers Table 1 20 Serial Port FPGA Pin Assignments DB9 Pin FPGA Pin Description 2 V14 TX 3 AA20 RX Table 1 21 Configuration Jumpers Jumper Function On Off JP1...

Page 35: ...P Switch FPGA Pin Assignments Switch No FPGA Pin Description 1 R26 FPGA_DIP_SW0 2 R25 FPGA_DIP_SW1 3 T23 FPGA_DIP_SW2 4 R24 FPGA_DIP_SW3 5 T18 FPGA_DIP_SW4 6 R22 FPGA_DIP_SW5 7 R21 FPGA_DIP_SW6 8 R20...

Page 36: ...le 1 25 0 1 3 Config Mode 0 see Table 1 25 0 1 2 Board flash memory fallback 0 Disabled 1 Enabled 1 System ACE configuration When the System ACE configuration is enabled the System ACE controller on t...

Page 37: ...rs Microphone line in line out and headphones connectors All connectors are stereo with the exception of the microphone connector SLAVE SELECTMAP CONFIG FROM XCF32P FLASH 1 1 0 SLAVE SERIAL CONFIG FRO...

Page 38: ...istered 512 MB DDR2 SDRAM The DDR2 SDRAM is usually a Micron MT8HTF6464HY 53E or similar Serial presence detection SPD through an I2C interface to the memory is also supported by the FPGA See DDR2 mem...

Page 39: ...Q_11 AC23 DDR2_A_12 N17 DDR2_0_DQ_12 V19 DDR2_A_13 N20 DDR2_0_DQ_13 V21 DDR2_0_BA_0 M23 DDR2_0_DQ_14 AA23 DDR2_0_BA_1 M21 DDR2_0_DQ_15 AC26 DDR2_0_BA_2 G24 DDR2_0_DQ_16 U20 DDR2_0_CAS_B G23 DDR2_0_DQ_...

Page 40: ...m ACE controller is enabled with the configuration DIP switches The board also features a System ACE failsafe mode Under this mode if the System ACE controller detects a failed configuration attempt i...

Page 41: ...address 0x01 for FMC connector 2 To write to the volatile section of the digital pot make sure that address 0x08 is set to 0x80 Use the following steps to configure the digital pot to the appropriate...

Page 42: ...44APW is used to separate those devices from one to the other Table 1 29 defines the various slave addresses accessible by the FPGA through the I2C MUX output Note To change the I2C MUX output you nee...

Page 43: ...62 0 1 1 0 0 0 1 R W DVI Monitor E DDC CI 0x6E 0 1 1 0 1 1 1 R W DVI Monitor E DDC 0xA0 1 0 1 0 0 0 0 R W DVI Monitor DDC Display Dependent Devices 0xFX 1 1 1 1 X X X R W Video Encoder 0xEC 1 1 1 0 1...

Page 44: ...44 www xilinx com Spartan 3A DSP 3400A Edition User Guide UG498 v2 2 November 17 2008 Chapter 1 Introduction R Downloaded from Elcodis com electronic components distributor...

Page 45: ...board flash memory the FPGA the CPLD the FMC expansion connector The chain bypasses the FMC expansion connector if no expansion module is present Jumper JP4 must not be populated for appropriate JTAG...

Page 46: ...The board flash memory can also be used to program the FPGA This memory can hold up to two configuration images or up to four with compression selectable with the two least significant bits of the co...

Page 47: ...hip to its factory default settings using the following equipment Xilinx download cable JTAG flying wires Downloading to the Spartan 3A DSP 3400A Edition Board 1 Connect a Xilinx download cable to the...

Page 48: ...t Execute XSVF SVF 6 To finish programming the chip cycle the power by turning off the board power switch 7 After turning the board back on verify that the clock frequencies are correct X Ref Target F...

Page 49: ...ting temperature range 0 C to 70 C non condensing Storage temperature range 55 C to 150 C non condensing Maximum Power Consumption The maximum power consumption is 6 84 W The power consumption specifi...

Page 50: ...50 www xilinx com XtremeDSP Spartan 3A DSP User Guide UG489 v2 2 November 17 2008 R Downloaded from Elcodis com electronic components distributor...

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