OPERATING AND USER MANUAL QUARTZ series CXP
26
Image acquisition (Icategory: AcquisitionControl)
6.4
The Quartz cameras have a buffered pipeline architecture, in which a FIFO memory decouples the
frame acquisition and the image interface transmission.
Regardless of trigger mode, image data follow a path through roughly three building blocks that can
have separate maximum data rates.
Camera buffered pipeline architecture.
Figure 6.2:
This architecture has a couple of implications.
The highest sustainable frame rate is limited by the slowest building block. The internal memory
•
(and FPGA) design is sufficiently fast such that it is never limiting. Depending on configuration,
the sensor or the interface limits the data rate and hence frame rate. This is elaborated in the next
sub sections.
For a limited amount of time the sensor acquisition frame rate may exceed the interface
•
transmission frame rate. During this time, the FIFO memory fills up. The memory size is 2^31 bit.
This corresponds to a total storage capacity of approximately 214 Mega pixel (memory storage of
pixels is always in 10bit).
The memory allows for advanced processing such as on-camera averaging (section 6.3.4).
•
The camera can be operated in a timed (continuous, free run) mode or in three different control
(triggered) modes that are explained in more detail in section (section 6.4.5).
Sensor acquisition speed
6.4.1.
The sensor always reads out entire lines. However, the amount of lines may be reduced increasing the
frame rate.
The maximum sensor frame rate (fps) can be calculated using the equation below.
The equation is valid for both the 2 Mp and the 4Mp sensor.
Note that in addition to image height H it also depends on the frame overhead O.
CAMERA
Q-2A340 / QR-2A340 / Q-4A180 / QR-4A180
Overhead (O)
27 us
Values of Overhead for different cameras.
Table 6.1:
Sensor
FIFO memory
Interface
