2
Remote Control
2.1 Remote control basis
19
Table 2.6 Description of Status Bytes
Data Bit
Meaning
0..1
Not used.
2
Error queue is not empty
This bit is set if a new error is inserted in the error queue. If the associated SRE bit enables
this bit and a new error is generated in the error queue, a service request is generated. This
identifies the error and queries the error message. This method effectively reduces errors
during program control.
3
Data sum bit of inquiry status register
This bit can only be set if the event bit of the inquiry status register is set and the associated
enable bit is set to 1. This bit represents a queriable instrument status. The specific status
information can be obtained by querying the inquiry status register of the status register.
4
M bit (message ailable)
This bit is set if the output queue information is readable. This bit is used when the controller
queries the instrument information.
5
ESB bit
Data sum bit of event status register. This bit can be set if one of the bits in the event status
register is set and the corresponding bit in the event status enable register is enabled. If this
bit is 1, it indicates that the instrument has experienced a serious error and you can obtain
specific error information by querying the event status register.
6
MSS bit (master status summary bit)
This bit is set if the instrument triggers a service request.
7
Operation status register data sum bit
This bit can be set if the event bit of the operation status register is set and the
corresponding enable bit is set to 1. This bit indicates that the instrument has executed an
operation. The specific operation type can be obtained by querying the operation status
register.
2) IST flag and Parallel Poll Enable Register (PPE)
The IST identifies the combination of the overall status of the instrument with a separate data bit. This
flag can be obtained by parallel query or by sending the command “*IST?”. The associated parallel query
enable register (PPE) determines which data bits of the STB act on the IST mark. The STB data bits
have the And relation with the PPE data bits, and the usage of bit6 is opposite to that in the SRE. The
IST flag is equal to the Or value of all results. Set and read the PPE through the command “*PRE” and
the command “*PRE?” respectively.
3) Event Status Register (ESR) and Event Status Enable Register (ESE)
or definition of ESR, refer to IEEE488.2. The event status register (ESR) can be read through the
command “*ESR?”. The ESE is an enable part of the SCPI register. If one position is set to 1 and one
data bit in the responsive ESR changes to 1 from 0, the ESB bit of the STB will be set to 1. Set and read
the ESE through the command “*ESE” and the command “*ESE?” respectively.
