68000 Motherboard User’s Manual
Rev. A
Page 19 of 54
The 68000 specifies the device to target for the bus transfer through its 24-bit addressing
scheme. The direction of the bus transfer, being either a Read of data into the processor
or a Write from the processor, is indicated through the Read/Write signal. The state of
this signal specifies whether the bus cycle is read or write, as defined relative to the
processor. With these signals established, the Address Strobe signal, /AS, is asserted.
This signals the target device and associated bus logic that address decoding may begin.
The address bus consists only of address bits A1-A23. It carries no A0 bit to distinguish
between the odd and even byte addresses that pair to make up the 16-bit data word. The
distinction between these is made though control signals /UDS and /LDS, the upper and
lower data strobes. The /UDS signal is asserted to include the most significant byte
(MSB) at the lower address, and /LDS is asserted to include the least significant byte
(LSB) at the next adjacent address. When the operation is 16-bit, both are asserted
together. This addressing mechanism is well suited to 16-bit buses that are typically
implemented as paired 8-bit devices.
6.4
Bus Control Signal Timing
Timing is everything. When negotiating the complex flow of data traffic, careful
management of the computer’s many interconnected devices is crucial.
6.4.1
Regular Bus Cycle Termination
Many microprocessors of the 1970’s operated more slowly than the peripheral and
memory devices with which they typically interfaced, so these processors simply initiated
a read or write operation at one phase in the bus cycle and unconditionally completed that
operation at a later phase in the cycle. This imposed an external limit on the processor
speed, in that the bus device must have completed its operation before the bus cycle
unconditionally closed along with the advancing system clock. The 68000, however, is
designed to decouple its clock speed from the speed of devices on the bus. It does this
through use of an acknowledge signal returned from the external logic that indicates to
the processor the completion of the bus operation. This handshaking signal is called the
Data Transfer Acknowledge. It uses negative logic and is abbreviated as /DTACK.
Motorola’s microprocessor literature refers to this means of bus control as asynchronous.
Read cycles require that the data has arrived and stabilized on the data bus before the
/DTACK signal is asserted. The requirement, therefore, is that the delay in generating
the /DTACK signal be greater than the delay in establishing the valid Read data on the
bus. This way, the processor is signaled that the data is available for it to proceed only
after the data signals are in fact available. But one exception arises here. Since /DTACK
is only examined on falling edges of the processor clock, this strict requirement is relaxed
if the two events do not straddle a falling clock edge. That is, if the data bus and
/DTACK signals are guaranteed to occur within the same clock period, with no falling
Summary of Contents for MB68k-100
Page 1: ...Rev A Grant K c 2011 ...