Reset
MSC711x Application Development System (MSC711xADS) Reference Manual, Rev. 1
Freescale Semiconductor
23
Board-Level Functions
3
This chapter discusses reset, clock, and power supply.
3.1 Reset
There are several reset sources on the MSC711XADS:
• Power-on reset for both the MSC711x and MPC8272 processors (
PORESET
).
• Manual hard reset for both the MSC711x and MPC8272 processors (
HRESET
).
• Manual soft reset for the MPC8272 processor (
SRESET
).
• MPC8272 internal sources (see also the MPC8272 PowerQUICC II™ Family Reference Manual).
• MSC711x internal sources (see also the MSC711x Reference Manual).
3.1.1
Power-On Reset
The power-on reset to the MPC8272 and MSC711x initializes the processor states after power-up. A dedicated
logic unit asserts
PORESET
input long enough stabilize the MSC711x and MPC8272 core voltages, powered by a
different voltage regulator. Power-on reset is either generated manually or by an on-board push button (SW3).
At the end of power-on reset, the MPC8272 samples the MODCK[1–3] bits to configure its various clock modes
(core, CPM, bus, PCI, and so on). The MODCK[1–3] combination options are selected by means of dip switches,
as described in Section 2.4.6, MPC8272 Clock Mode Settings (SW8), on page 15.
After deassertion of power-on reset, the hard-reset sequence starts. During the hard-reset sequence, many options
are configured. Some of these options are additional clock configuration bits in MODCKH[0–3]. These bits are the
most significant bits of the MODCK field, which determine additional options for the clock generator. Although
these bits are sampled when the hard reset sequence is entered, they are influential only once: immediately after
power-on reset. If a hard reset sequence is entered later, MODCKH[0–3] are sampled but no action is taken.
The PCI_MODCK signal is sampled concurrently with the MODCK[0–3] bits and determines the PCI bus clock
frequency. When it is asserted high, it divides the PCI bus frequency by two. When it is asserted low, the PCI bus
frequency is as determined by the
MODCK[1–3]
and MODCKH[0–3] signals.
At the rising edge of the power-on signal, the MSC711x processor samples four pins to determine its configuration.
Those pins are
BM0
,
BM1
,
SWTE
, and
HDPOL
. These pins are sampled only once immediately after
PORESET
is
deasserted.
3.1.2
Hard Reset
Any one of the following sources can generate a hard reset on the MSC711xADS:
• COP/JTAG port. Asserting the
HRESET
line connected to the COP/JTAG port connector directly generates a
hard-reset for both the MPC8272 and MSC711x devices, depending on the JP6 position.
