MSC711x Application Development System (MSC711xADS) Reference Manual, Rev. 1
40
Freescale Semiconductor
MSC711xADS Interfaces
5.2 60x Bus Buffering
For best MSC711xADS performance, the capacitive load over the 60x bus must be reduced as much as possible.
Therefore, the slower devices on the bus, such as the Flash memory, HDI interface, BCSR, and E1/T1 framer, are
buffered. The SDRAM is not buffered. To reduce noise and reflections further, serial damping resistors are placed
over SDRAM addresses and all MPC8272 strobe lines. The data transceivers are open only if there is an access to
a valid buffered board address or during hard reset configuration. Data conflicts are avoided for unbuffered
memory reads or off-board memory reads, if they are not mapped to a valid address on the board. It is the user’s
responsibility to prevent such errors.
5.3 MSC711x Connection to the MPC8272
Figure 5-2 shows the data and signal connections between the MSC711x device and the host (MPC8272). The data
and address lines are buffered, but the control signals (read/write, acknowledge, and so on) are transferred via the
Board Control and Status Register (BCSR). For details on the BCSR, see Chapter 4, Memory Map/Programming
Model, on page 29.
Figure 5-2. MSC711x Connection to the MPC8272
30
HDS
I
Host Read/Write or Host Read Input.
31
HRESET
I/O, P.U
MSC7116 Hard Reset.
32
PORESET
I/O, P.U
Power-On-Reset.
33
3V3
P
+3.3V Power Out. These lines are connected to the main 3.3 V plane of the
MSC711xEVM.
34
NC
—
Not connected.
35
GND
P
Digital GND. Main GND plane.
36
Table 5-1. Host Interface Connector Pins (Continued)
Pin
Signal Name
Attribute
Description
MPC8272
MSC711x
Buffer
BCSR
60x Bus D[0–15]
60x Bus A[28–30]
CS
R/W
BBCTL0
IDMA
60x Bus D[0–15]
60x Bus A[28-30]
BCS
HRW
HDS
HDDS
HREQ
HACK
HREQ
HACK
HDDS
HDS
HRW
CS
HD[15–0]
HA[2–0]
