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Silicon Laboratories C8051F120, Manual

Download the free user manual for the Silicon Laboratories C8051F120 at 88.208.23.73:8080. This comprehensive manual provides detailed instructions and insights into this advanced product, helping you maximize its capabilities. Accessible for free, the manual is your invaluable resource to fully understand and utilize the C8051F120's features.

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C8051F120/1/2/3/4/5/6/7

Rev. 1.2

195

likely to be interrupted repeatedly (such as a code loop that is waiting for an interrupt to happen). Instructions that are
part of an interrupt service routine (ISR) can also be excluded from caching. By default, ISR instructions are cached,
but this can be disabled by clearing the CHISR bit (CCH0CN.2) to ‘0’.  The other information that can be explicitly
excluded from caching are the data returned by MOVC instructions.  Clearing the CHMOV bit (CCH0CN.1) to ‘0’
will disable caching of MOVC data. If MOVC caching is allowed, it can be restricted to only use slot 0 for the
MOVC information (excluding cache push operations). The CHFIXM bit (CCH0TN.2) controls this behavior.

Further cache control can be implemented by disabling all cache writes.  Cache writes can be disabled by clearing the
CHWREN bit (CCH0CN.7) to ‘0’. Although normal cache writes (such as those after a cache miss) are disabled, data
can still be written to the cache with a cache push operation.  Disabling cache writes can be used to prevent a non-crit-
ical section of code from changing the cache contents.  Note that regardless of the value of CHWREN, a FLASH
write or erase operation automatically removes the affected bytes from the cache. Cache reads and the prefetch engine
can also be individually disabled. Disabling cache reads forces all instructions data to execute from FLASH memory
or from the prefetch engine. To disable cache reads, the CHRDEN bit (CCH0CN.6) can be cleared to ‘0’.  Note that
when cache reads are disabled, cache writes will still occur (if CHWREN is set to ‘1’).  Disabling the prefetch engine
is accomplished using the CHPFEN bit (CCH0CN.5).  When this bit is cleared to ‘0’, the prefetch engine will be dis-
abled.  If both CHPFEN and CHRDEN are ‘0’, code will execute at a fixed rate, as instructions become available
from the FLASH memory.

Cache locations can also be pre-loaded and locked with time-critical branch destinations.  For example, in a system
with an ISR that must respond as fast as possible, the entry point for the ISR can be locked into a cache location to
minimize the response latency of the ISR. Up to 61 locations can be locked into the cache at one time.  Instructions
are locked into cache by enabling cache push operations with the CHPUSH bit (CCH0LC.7).  When CHPUSH is set
to ‘1’, a MOVC instruction will cause the four-byte segment containing the data byte to be written to the cache slot
location indicated by CHSLOT (CCH0LC.5-0).  CHSLOT is them decremented to point to the next lockable cache
location.  This process is called a cache push operation. Cache locations that are above CHSLOT are “locked”, and
cannot be changed by the processor core, as shown in Figure 17.3.  Cache locations can be unlocked by using a cache
pop operation.  A cache pop is performed by writing a ‘1’ to the CHPOP bit (CCH0LC.6).  When a cache pop is ini-
tiated, the value of CHSLOT is incremented. This unlocks the most recently locked cache location, but does not
remove the information from the cache. Note that a cache pop should not be initiated if CHSLOT is equal to 111110b.
Doing so may have an adverse effect on cache performance. 

Important: Although locking cache location 1 is not

explicitly disabled by hardware, the entire cache will be unlocked when CHSLOT is equal to 000000b.  There-
fore, cache locations 1 and 0 must remain unlocked at all times.

TAG 62

SLOT 62

TAG 61

SLOT 61

TAG 2

SLOT 2

TAG 1

SLOT 1

TAG 0

SLOT 0

TAG 60

SLOT 60

TAG 59

SLOT 59

CHSLOT = 58

LOCKED

LOCKED

LOCKED

UNLOCKED

UNLOCKED

UNLOCKED

Lock Status

Cache Push

Operations
Decrement

CHSLOT

Cache Pop
Operations

Increment

CHSLOT

LOCKED

TAG 58

SLOT 58

UNLOCKED

UNLOCKED

TAG 57

SLOT 57

UNLOCKED

Figure 17.3. Cache Lock Operation

Summary of Contents for C8051F120

Page 1: ...f Instruction Set in 1 or 2 System Clocks Up to 100 MIPS C8051F120 1 2 3 or 50 MIPS C8051F124 5 6 7 Throughput using Integrated PLL 2 cycle 16 x 16 MAC Engine C8051F120 1 2 3 Flexible Interrupt Sources MEMORY 8448 Bytes Internal Data RAM 8k 256 128k Bytes Banked FLASH In System programmable in 1024 byte Sectors External 64k Byte Data Memory Interface programma ble multiplexed or non multiplexed mo...

Page 2: ...C8051F120 1 2 3 4 5 6 7 2 Rev 1 2 Notes ...

Page 3: ... BIT ADC C8051F120 1 4 5 ONLY 49 5 1 Analog Multiplexer and PGA 49 5 2 ADC Modes of Operation 51 5 2 1 Starting a Conversion 51 5 2 2 Tracking Modes 52 5 2 3 Settling Time Requirements 53 5 3 ADC0 Programmable Window Detector 60 6 ADC0 10 BIT ADC C8051F122 3 6 7 ONLY 67 6 1 Analog Multiplexer and PGA 67 6 2 ADC Modes of Operation 69 6 2 1 Starting a Conversion 69 6 2 2 Tracking Modes 70 6 2 3 Sett...

Page 4: ...R Paging 128 12 2 6 3 SFR Page Stack Example 130 12 2 7 Register Descriptions 143 12 3 Interrupt Handler 146 12 3 1 MCU Interrupt Sources and Vectors 146 12 3 2 External Interrupts 146 12 3 3 Interrupt Priorities 148 12 3 4 Interrupt Latency 148 12 3 5 Interrupt Register Descriptions 149 12 4 Power Management Modes 155 12 4 1 Idle Mode 155 12 4 2 Stop Mode 155 13 MULTIPLY AND ACCUMULATE MAC0 157 1...

Page 5: ...LASH Memory From Software 187 16 2 Security Options 188 17 BRANCH TARGET CACHE 193 17 1 Cache and Prefetch Operation 193 17 2 Cache and Prefetch Optimization 194 18 EXTERNAL DATA MEMORY INTERFACE AND ON CHIP XRAM 199 18 1 Accessing XRAM 199 18 1 1 16 Bit MOVX Example 199 18 1 2 8 Bit MOVX Example 199 18 2 Configuring the External Memory Interface 199 18 3 Port Selection and Configuration 200 18 4 ...

Page 6: ... 19 2 3 Configuring Port Pins as Digital Inputs 232 19 2 4 Weak Pull ups 232 19 2 5 External Memory Interface 232 20 SYSTEM MANAGEMENT BUS I2C BUS SMBUS0 237 20 1 Supporting Documents 238 20 2 SMBus Protocol 238 20 2 1 Arbitration 239 20 2 2 Clock Low Extension 239 20 2 3 SCL Low Timeout 239 20 2 4 SCL High SMBus Free Timeout 239 20 3 SMBus Transfer Modes 240 20 3 1 Master Transmitter Mode 240 20 ...

Page 7: ...0 13 bit Counter Timer 285 24 1 2 Mode 1 16 bit Counter Timer 286 24 1 3 Mode 2 8 bit Counter Timer with Auto Reload 287 24 1 4 Mode 3 Two 8 bit Counter Timers Timer 0 Only 288 24 2 Timer 2 Timer 3 and Timer 4 293 24 2 1 Configuring Timer 2 3 and 4 to Count Down 293 24 2 2 Capture Mode 294 24 2 3 Auto Reload Mode 295 24 2 4 Toggle Output Mode Timer 2 and Timer 4 Only 295 25 PROGRAMMABLE COUNTER AR...

Page 8: ...C8051F120 1 2 3 4 5 6 7 8 Rev 1 2 26 2 Flash Programming Commands 318 26 3 Debug Support 321 ...

Page 9: ...ram 49 Figure 5 2 Typical Temperature Sensor Transfer Function 50 Figure 5 3 ADC0 Track and Conversion Example Timing 52 Figure 5 4 ADC0 Equivalent Input Circuits 53 Figure 5 5 AMX0CF AMUX0 Configuration Register 54 Figure 5 6 AMX0SL AMUX0 Channel Select Register 55 Figure 5 7 ADC0CF ADC0 Configuration Register 56 Figure 5 8 ADC0CN ADC0 Control Register 57 Figure 5 9 ADC0H ADC0 Data Word MSB Regis...

Page 10: ...igure 6 19 10 Bit ADC0 Window Interrupt Example Left Justified Differential Data 83 7 ADC2 8 BIT ADC 85 Figure 7 1 ADC2 Functional Block Diagram 85 Figure 7 2 ADC2 Track and Conversion Example Timing 87 Figure 7 3 ADC2 Equivalent Input Circuit 88 Figure 7 4 AMX2CF AMUX2 Configuration Register 89 Figure 7 5 AMX2SL AMUX2 Channel Select Register 90 Figure 7 6 ADC2CF ADC2 Configuration Register 91 Fig...

Page 11: ...age Stack Upon Return From PCA Interrupt 133 Figure 12 10 SFR Page Stack Upon Return From ADC2 Window Interrupt 134 Figure 12 11 SFRPGCN SFR Page Control Register 135 Figure 12 12 SFRPAGE SFR Page Register 135 Figure 12 13 SFRNEXT SFR Next Register 136 Figure 12 14 SFRLAST SFR Last Register 136 Figure 12 15 SP Stack Pointer 143 Figure 12 16 DPL Data Pointer Low Byte 143 Figure 12 17 DPH Data Point...

Page 12: ... 15 2 OSCICL Internal Oscillator Calibration Register 174 Figure 15 3 OSCICN Internal Oscillator Control Register 174 Figure 15 4 CLKSEL System Clock Selection Register 175 Figure 15 5 OSCXCN External Oscillator Control Register 176 Figure 15 6 PLL Block Diagram 178 Figure 15 7 PLL0CN PLL Control Register 180 Figure 15 8 PLL0DIV PLL Pre divider Register 180 Figure 15 9 PLL0MUL PLL Clock Scaler Reg...

Page 13: ...23 Figure 19 7 XBR0 Port I O Crossbar Register 0 224 Figure 19 8 XBR1 Port I O Crossbar Register 1 225 Figure 19 9 XBR2 Port I O Crossbar Register 2 226 Figure 19 10 P0 Port0 Data Register 227 Figure 19 11 P0MDOUT Port0 Output Mode Register 227 Figure 19 12 P1 Port1 Data Register 228 Figure 19 13 P1MDIN Port1 Input Mode Register 228 Figure 19 14 P1MDOUT Port1 Output Mode Register 229 Figure 19 15 ...

Page 14: ...I0 Data Register 259 Figure 21 12 SPI Master Timing CKPHA 0 260 Figure 21 13 SPI Master Timing CKPHA 1 260 Figure 21 14 SPI Slave Timing CKPHA 0 261 Figure 21 15 SPI Slave Timing CKPHA 1 261 22 UART0 263 Figure 22 1 UART0 Block Diagram 263 Figure 22 2 UART0 Mode 0 Timing Diagram 264 Figure 22 3 UART0 Mode 0 Interconnect 264 Figure 22 4 UART0 Mode 1 Timing Diagram 265 Figure 22 5 UART0 Modes 2 and ...

Page 15: ...Timer 2 3 and 4 High Byte 300 25 PROGRAMMABLE COUNTER ARRAY 301 Figure 25 1 PCA Block Diagram 301 Figure 25 2 PCA Counter Timer Block Diagram 302 Figure 25 3 PCA Interrupt Block Diagram 303 Figure 25 4 PCA Capture Mode Diagram 304 Figure 25 5 PCA Software Timer Mode Diagram 305 Figure 25 6 PCA High Speed Output Mode Diagram 306 Figure 25 7 PCA Frequency Output Mode 307 Figure 25 8 PCA 8 Bit PWM Mo...

Page 16: ...C8051F120 1 2 3 4 5 6 7 16 Rev 1 2 Notes ...

Page 17: ...051F120 2 4 6 107 Table 9 1 Voltage Reference Electrical Characteristics 108 10 VOLTAGE REFERENCE C8051F121 3 5 7 109 Table 10 1 Voltage Reference Electrical Characteristics 110 11 COMPARATORS 111 Table 11 1 Comparator Electrical Characteristics 118 12 CIP 51 MICROCONTROLLER 119 Table 12 1 CIP 51 Instruction Set Summary 121 Table 12 2 Special Function Register SFR Memory Map 137 Table 12 3 Special...

Page 18: ...ttings for Standard Baud Rates Using The Internal Oscillator 282 Table 23 2 Timer Settings for Standard Baud Rates Using an External Oscillator 282 Table 23 3 Timer Settings for Standard Baud Rates Using an External Oscillator 283 Table 23 4 Timer Settings for Standard Baud Rates Using the PLL 283 Table 23 5 Timer Settings for Standard Baud Rates Using the PLL 284 24 TIMERS 285 25 PROGRAMMABLE COU...

Page 19: ...Counter Timer Array with 6 capture compare modules On chip Watchdog Timer VDD Monitor and Temperature Sensor With on chip VDD monitor Watchdog Timer and clock oscillator the C8051F12x devices are truly stand alone Sys tem on a Chip solutions All analog and digital peripherals are enabled disabled and configured by user firmware The FLASH memory can be reprogrammed even in circuit providing non vol...

Page 20: ...olution bits DAC Outputs Analog Comparators Package C8051F120 100 128k 8448 3 3 3 3 2 5 3 64 8 8 3 3 12 2 2 100TQFP C8051F121 100 128k 8448 3 3 3 3 2 5 3 32 8 8 3 3 12 2 2 64TQFP C8051F122 100 128k 8448 3 3 3 3 2 5 3 64 8 8 3 3 12 2 2 100TQFP C8051F123 100 128k 8448 3 3 3 3 2 5 3 32 8 8 3 3 12 2 2 64TQFP C8051F124 50 128k 8448 3 3 3 2 5 3 64 8 8 3 3 12 2 2 100TQFP C8051F125 50 128k 8448 3 3 3 2 5 ...

Page 21: ...l Power Analog Power Debug HW Boundary Scan 8kbyte XRAM P2 0 P2 7 P1 0 AIN2 0 P1 7 AIN2 7 P0 0 P0 7 P1 Drv P2 Drv Data Bus Address Bus Bus Control DAC1 DAC1 12 Bit VREF DAC0 12 Bit ADC 100ksps 12 Bit A M U X AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 DAC0 CP0 CP0 CP1 CP1 VREF TEMP SENSOR UART0 P3 0 P3 7 P3 Drv 8 1 MONEN WDT VREFD VREF0 Prog Gain CP0 CP1 C T L P4 Latch D a t a P7 Latch...

Page 22: ...2 Drv Data Bus Address Bus Bus Control DAC1 DAC1 12 Bit VREF DAC0 12 Bit ADC 100ksps 12 Bit A M U X AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 DAC0 CP0 CP0 CP1 CP1 VREF TEMP SENSOR UART0 P3 0 P3 7 P3 Drv 8 1 MONEN WDT VREFA Prog Gain CP0 CP1 C T L P4 Latch D a t a P7 Latch A d d r P5 Latch P6 Latch P7 DRV P5 DRV P6 DRV P4 DRV Prog Gain ADC 500ksps 8 Bit A M U X VREFA AV XTAL1 XTAL2 Ex...

Page 23: ...0ksps 10 Bit A M U X AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 DAC0 CP0 CP0 CP1 CP1 VREF TEMP SENSOR UART0 P3 0 P3 7 P3 Drv 8 1 MONEN WDT VREFD VREF0 Prog Gain CP0 CP1 C T L P4 Latch D a t a P7 Latch A d d r P5 Latch P6 Latch P7 0 D0 P7 7 D7 P7 DRV P5 0 A8 P5 7 A15 P5 DRV P6 0 A0 P6 7 A7 P6 DRV P4 DRV P4 5 ALE P4 6 RD P4 7 WR P4 0 P4 4 Prog Gain ADC 500ksps 8 Bit A M U X VREF2 XTAL1 ...

Page 24: ...DAC1 DAC1 12 Bit VREF DAC0 12 Bit ADC 100ksps 10 Bit A M U X AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 DAC0 CP0 CP0 CP1 CP1 VREF TEMP SENSOR UART0 P3 0 P3 7 P3 Drv 8 1 MONEN WDT VREFA Prog Gain CP0 CP1 C T L P4 Latch D a t a P7 Latch A d d r P5 Latch P6 Latch P7 DRV P5 DRV P6 DRV P4 DRV Prog Gain ADC 500ksps 8 Bit A M U X VREFA AV XTAL1 XTAL2 External Oscillator Circuit System Clock ...

Page 25: ...pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture In a standard 8051 all instructions except for MUL and DIV take 12 or 24 system clock cycles to exe cute with a maximum system clock of 12 to 24 MHz By contrast the CIP 51 core executes 70 of its instructions in one or two system clock cycles with only four instructions taking more than fou...

Page 26: ...disabled by the user in software the VDD monitor is enabled disabled via the MONEN pin The Watchdog Timer may be perma nently enabled in software after a power on reset during MCU initialization The MCU has an internal stand alone clock generator which is used by default as the system clock after any reset If desired the clock source may be switched on the fly to the external oscillator which can ...

Page 27: ...to 8k directed to on chip above 8k directed to EMIF The EMIF is also configurable for multiplexed or non multiplexed address data lines The MCU s program memory consists of 128k bytes of banked FLASH memory This memory may be repro grammed in system in 1024 byte sectors and requires no special off chip programming voltage The 1024 bytes from addresses 0x1FC00 to 0x1FFFF are reserved There are also...

Page 28: ... studio and debugger an integrated 8051 assembler and an RS 232 to JTAG serial adapter It also has a target application board with the associated MCU installed plus the RS 232 and JTAG cables and wall mount power supply The Develop ment Kit requires a Windows 95 98 NT ME computer with one available RS 232 serial port As shown in Figure 1 7 the PC is connected via RS 232 to the Serial Adapter A six...

Page 29: ... rounding engine provides a rounded 16 bit fractional result after an additional third SYSCLK cycle MAC0 also contains a 1 bit arithmetic shifter that will left or right shift the contents of the 40 bit accumulator in a single SYSCLK cycle MAC0CF MAC0MS MAC0FM MAC0SAT MAC0CA MAC0SD MAC0SC MAC0STA MAC0N MAC0SO MAC0Z MAC0HO 16 x 16 Multiply MAC0RNDH MAC0RNDL MAC0 Rounding Register MAC0OVR MAC0ACC3 M...

Page 30: ... all combinations of functions are supported The on chip counter timers serial buses HW interrupts ADC Start of Conversion inputs comparator outputs and other digital signals in the controller can be configured to appear on the Port I O pins specified in the Crossbar Con trol registers This allows the user to select the exact mix of general purpose Port I O and digital resources needed for the par...

Page 31: ...he external oscillator source divided by 8 Each capture compare module can be configured to operate in one of six modes Edge Triggered Capture Software Timer High Speed Output Frequency Output 8 Bit Pulse Width Modulator or 16 Bit Pulse Width Modulator The PCA Capture Compare Module I O and External Clock Input are routed to the MCU Port I O via the Digital Cross bar Capture Compare Module 1 Captu...

Page 32: ...us and SMBus I2C Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP 51 s interrupts thus requiring very little intervention by the CPU The serial buses do not share resources such as timers interrupts or Port I O so any or all of the serial buses may be used together with any other ...

Page 33: ... 2 The gain stage can be especially useful when different ADC input channels have widely varied input voltage signals or when it is necessary to zoom in on a signal with a large DC offset in differential mode a DAC could be used to provide the DC offset Conversions can be started in four ways a software command an overflow of Timer 2 an overflow of Timer 3 or an external signal input This flexibil...

Page 34: ...ut channels have widely varied input voltage signals or when it is necessary to zoom in on a signal with a large DC offset in differential mode a DAC could be used to provide the DC offset The PGA gain can be set in software to 0 5 1 2 or 4 A flexible conversion scheduling system allows ADC2 conversions to be initiated by software commands timer overflows or an external input signal ADC2 conversio...

Page 35: ...eep mode The com parators output state can also be polled in software The comparator outputs can be programmed to appear on the Port I O pins via the Crossbar The DACs are voltage output mode and include a flexible output scheduling mechanism This scheduling mecha nism allows DAC output updates to be forced by a software write or a Timer 2 3 or 4 overflow The DAC voltage reference is supplied via ...

Page 36: ...gh VDD AV DGND and AGND 800 mA Maximum output current sunk by any Port pin 100 mA Maximum output current sunk by any other I O pin 50 mA Maximum output current sourced by any Port pin 100 mA Maximum output current sourced by any other I O pin 50 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operati...

Page 37: ... Digital Supply Current with CPU active VDD 3 0 V Clock 100 MHz VDD 2 7 V Clock 50 MHz VDD 2 7 V Clock 1 MHz VDD 2 7 V Clock 32 kHz TBD 25 0 6 16 mA mA mA µA Digital Supply Current with CPU inactive not accessing FLASH VDD 3 0 V Clock 100 MHz VDD 2 7 V Clock 50 MHz VDD 2 7 V Clock 1 MHz VDD 2 7 V Clock 32 kHz TBD TBD TBD TBD mA mA mA µA Digital Supply Current shut down Oscillator not running TBD µ...

Page 38: ...Supply Current with CPU active VDD 2 7 V Clock 50 MHz VDD 2 7 V Clock 1 MHz VDD 2 7 V Clock 32 kHz 25 0 6 16 mA mA µA Digital Supply Current with CPU inactive not accessing FLASH VDD 2 7 V Clock 50 MHz VDD 2 7 V Clock 1 MHz VDD 2 7 V Clock 32 kHz 16 0 3 TBD mA mA µA Digital Supply Current shut down Oscillator not running 0 4 µA Digital Supply RAM Data Retention Voltage 1 5 V SYSCLK System Clock No...

Page 39: ...r Is driven low when VDD is VRST and MONEN is high An external source can initiate a system reset by driving this pin low XTAL1 26 17 A In Crystal Input This pin is the return for the internal oscillator circuit for a crystal or ceramic resonator For a precision internal clock connect a crystal or ceramic resonator from XTAL1 to XTAL2 If overdriven by an external CMOS clock this becomes the system...

Page 40: ...0 8 3 A In Comparator 0 Inverting Input CP1 7 2 A In Comparator 1 Non Inverting Input CP1 6 1 A In Comparator 1 Inverting Input DAC0 100 64 A Out Digital to Analog Converter 0 Voltage Output See DAC Specifica tion for complete description DAC1 99 63 A Out Digital to Analog Converter 1 Voltage Output See DAC Specifica tion for complete description P0 0 62 55 D I O Port 0 0 See Port Input Output sec...

Page 41: ...N2 5 A13 P1 5 31 22 A In D I O Port 1 5 See Port Input Output section for complete description AIN2 6 A14 P1 6 30 21 A In D I O Port 1 6 See Port Input Output section for complete description AIN2 7 A15 P1 7 29 20 A In D I O Port 1 7 See Port Input Output section for complete description A8m A0 P2 0 46 37 D I O Bit 8 External Memory Address bus Multiplexed mode Bit 0 External Memory Address bus No...

Page 42: ...n for complete description P4 1 97 D I O Port 4 1 See Port Input Output section for complete description P4 2 96 D I O Port 4 2 See Port Input Output section for complete description P4 3 95 D I O Port 4 3 See Port Input Output section for complete description P4 4 94 D I O Port 4 4 See Port Input Output section for complete description ALE P4 5 93 D I O ALE Strobe for External Memory Address bus ...

Page 43: ...5 D I O Port 6 5 See Port Input Output section for complete description A14m A6 P6 6 74 D I O Port 6 6 See Port Input Output section for complete description A15m A7 P6 7 73 D I O Port 6 7 See Port Input Output section for complete description AD0 D0 P7 0 72 D I O Bit 0 External Memory Address Data bus Multiplexed mode Bit 0 External Memory Data bus Non multiplexed mode Port 7 0 See Port Input Out...

Page 44: ...0 D0 P7 0 AD1 D1 P7 1 AD2 D2 P7 2 AD3 D3 P7 3 AD4 D4 P7 4 AD5 D5 P7 5 DAC0 DAC1 P4 0 P4 1 P4 2 P4 3 P4 4 ALE P4 5 RD P4 6 WR P4 7 VDD DGND A8 P5 0 A9 P5 1 A10 P5 2 A11 P5 3 A12 P5 4 A13 P5 5 A14 P5 6 A15 P5 7 A8m A0 P6 0 A9m A1 P6 1 A10m A2 P6 2 A11m A3 P6 3 A12m A4 P6 4 AGND AV VREF AGND AV VREFD VREF0 VREF2 AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 TMS TCK TDI TDO RST CP1 CP1 CP0 C...

Page 45: ... 4 5 6 7 Rev 1 2 45 A A1 A2 b D D1 e E E1 0 05 0 95 0 17 1 00 0 22 16 00 14 00 0 50 16 00 14 00 1 20 0 15 1 05 0 27 MIN mm NOM mm MAX mm 100 e A1 b A2 A PIN 1 DESIGNATOR 1 E1 E D1 D Figure 4 2 TQFP 100 Package Drawing ...

Page 46: ...3 P0 4 ALE P0 5 RD P0 6 WR P0 7 AD0 D0 P3 0 AD1 D1 P3 1 AD2 D2 P3 2 AD3 D3 P3 3 AD4 D4 P3 4 AD5 D5 P3 5 VDD DGND AD6 D6 P3 6 AD7 D7 P3 7 A8m A0 P2 0 A9m A1 P2 1 A10m A2 P2 2 A11m A3 P2 3 A12m A4 P2 4 CP1 CP1 CP0 CP0 AGND AV VREF VREFA AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 XTAL1 XTAL2 MONEN AIN2 7 A15 P1 7 AIN2 6 A14 P1 6 AIN2 5 A13 P1 5 AIN2 4 A12 P1 4 VDD DGND AIN2 3 A11 P1 3 AI...

Page 47: ...2 3 4 5 6 7 Rev 1 2 47 A A1 A2 b D D1 e E E1 0 05 0 95 0 17 0 22 12 00 10 00 0 50 12 00 10 00 1 20 0 15 1 05 0 27 MIN mm NOM mm MAX mm 1 64 E E1 e A1 b D D1 PIN 1 DESIGNATOR A2 A Figure 4 4 TQFP 64 Package Drawing ...

Page 48: ...C8051F120 1 2 3 4 5 6 7 48 Rev 1 2 ...

Page 49: ...sfer function is shown in Figure 5 2 AMUX input pairs can be programmed to operate in either differential or single ended mode This allows the user to select the best measure ment technique for each input channel and even accommodates mode changes on the fly The AMUX defaults to all single ended inputs upon reset There are two registers associated with the AMUX the Channel Selection register AMX0S...

Page 50: ...PGA input when the Temperature Sensor is selected by bits AMX0AD3 0 in register AMX0SL this voltage will be amplified by the PGA according to the user programmed PGA settings 0 50 50 100 Celsius 0 500 0 600 0 700 0 800 0 900 Volts VTEMP 0 00286 TEMPC 0 776 for PGA Gain 1 1 000 Figure 5 2 Typical Temperature Sensor Transfer Function ...

Page 51: ...on is complete The fall ing edge of AD0BUSY triggers an interrupt when enabled and sets the AD0INT interrupt flag ADC0CN 5 Con verted data is available in the ADC0 data word MSB and LSB registers ADC0H ADC0L Converted data can be either left or right justified in the ADC0H ADC0L register pair see example in Figure 5 11 depending on the pro grammed state of the AD0LJST bit in the ADC0CN register Wh...

Page 52: ...n when the entire chip is in low power standby or sleep modes Low power track and hold mode is also useful when AMUX or PGA settings are frequently changed to ensure that settling time requirements are met see Section 5 2 3 Settling Time Requirements on page 53 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CNVSTR0 AD0CM 1 0 10 ADC0TM 1 ADC0TM 0 Timer 2 Timer 3 Overflow Write 1 to AD0BUSY AD0CM 1 0 00 01 ...

Page 53: ... Temperature Sensor output RTOTAL reduces to RMUX An absolute minimum settling time of 1 5 µs is required after any MUX or PGA selection Note that in low power tracking mode three SAR clocks are used for tracking at the start of every conversion For most applications these three SAR clocks will meet the tracking requirements Where SA is the settling accuracy given as a fraction of an LSB for examp...

Page 54: ...are respectively differential input pair Bit1 AIN23IC AIN0 2 AIN0 3 Input Pair Configuration Bit 0 AIN0 2 and AIN0 3 are independent single ended inputs 1 AIN0 2 AIN0 3 are respectively differential input pair Bit0 AIN01IC AIN0 0 AIN0 1 Input Pair Configuration Bit 0 AIN0 0 and AIN0 1 are independent single ended inputs 1 AIN0 0 AIN0 1 are respectively differential input pair NOTE The ADC0 Data Wo...

Page 55: ...AIN0 6 AIN0 7 TEMP SENSOR 0100 AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 TEMP SENSOR 0101 AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 TEMP SENSOR 0110 AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 TEMP SENSOR 0111 AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 TEMP SENSOR 1000 AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 TEMP SENSOR 1001 AIN0...

Page 56: ...onversion Clock should be less than or equal to 2 5 MHz When the AD0SC bits are equal to 00000b the SAR Conversion clock is equal to SYSCLK to facili tate faster ADC conversions at slower SYSCLK speeds Bits2 0 AMP0GN2 0 ADC0 Internal Amplifier Gain PGA 000 Gain 1 001 Gain 2 010 Gain 4 011 Gain 8 10x Gain 16 11x Gain 0 5 SFR Page SFR Address 0 0xBC R W R W R W R W R W R W R W R W Reset Value AD0SC4...

Page 57: ... of 1 to AD0BUSY 01 ADC0 conversion initiated on overflow of Timer 3 10 ADC0 conversion initiated on rising edge of external CNVSTR0 11 ADC0 conversion initiated on overflow of Timer 2 If AD0TM 1 00 Tracking starts with the write of 1 to AD0BUSY and lasts for 3 SAR clocks followed by con version 01 Tracking started by the overflow of Timer 3 and lasts for 3 SAR clocks followed by conversion 10 ADC...

Page 58: ...ata Word SFR Page SFR Address 0 0xBF R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Figure 5 10 ADC0L ADC0 Data Word LSB Register Bits7 0 ADC0 Data Word Low Order Bits For AD0LJST 0 Bits 7 0 are the lower 8 bits of the 12 bit ADC0 Data Word For AD0LJST 1 Bits 7 4 are the lower 4 bits of the 12 bit ADC0 Data Word Bits3 0 will always read 0 SFR Page SFR ...

Page 59: ... 0x00 AMX0SL 0x00 Example ADC0 Data Word Conversion Map AIN0 0 AIN0 1 Differential Input Pair AMX0CF 0x01 AMX0SL 0x00 For AD0LJST 0 n 12 for Single Ended n 11 for Differential AIN0 0 AGND Volts ADC0H ADC0L AD0LJST 0 ADC0H ADC0L AD0LJST 1 VREF 4095 4096 0x0FFF 0xFFF0 VREF 2 0x0800 0x8000 VREF 2047 4096 0x07FF 0x7FF0 0 0x0000 0x0000 AIN0 0 AIN0 1 Volts ADC0H ADC0L AD0LJST 0 ADC0H ADC0L AD0LJST 1 VRE...

Page 60: ...0 Less Than registers ADC0GTH ADC0GTL ADC0LTH and ADC0LTL Reference comparisons are shown starting on page 62 Notice that the window detector flag can be asserted when the measured data is inside or outside the user programmed limits depending on the programming of the ADC0GTx and ADC0LTx registers Figure 5 12 ADC0GTH ADC0 Greater Than Data High Byte Register Bits7 0 High byte of ADC0 Greater Than...

Page 61: ...Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Figure 5 14 ADC0LTH ADC0 Less Than Data High Byte Register Figure 5 15 ADC0LTL ADC0 Less Than Data Low Byte Register Bits7 0 Low byte of ADC0 Less Than Data Word SFR Page SFR Address 0 0xC6 R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ...

Page 62: ...0 ADC0GTH ADC0GTL 0x0200 An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt AD0WINT 1 if the resulting ADC0 Data Word is 0x0200 or 0x0100 0x0FFF 0x0201 0x0200 0x01FF 0x0101 0x0100 0x00FF 0x0000 AD0WINT 1 AD0WINT not affected AD0WINT not affected ADC Data Word 0x0FFF 0x0201 0x0200 0x01FF 0x0101 0x0100 0x00FF 0x0000 AD0WINT 1 AD0WINT not affected AD0WINT 1 ADC0LTH ADC0LTL ADC0GTH ...

Page 63: ... 1 REF x 2047 2048 REF x 256 2048 REF x 1 2048 Figure 5 17 12 Bit ADC0 Window Interrupt Example Right Justified Differential Data Given AMX0SL 0x00 AMX0CF 0x01 AD0LJST 0 ADC0LTH ADC0LTL 0x0100 ADC0GTH ADC0GTL 0xFFFF An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt AD0WINT 1 if the resulting ADC0 Data Word is 0x0100 and 0xFFFF In two s complement math 0xFFFF 1 Given AMX0SL 0x00...

Page 64: ...12 4096 0 Input Voltage AD0 0 AGND REF x 4095 4096 REF x 256 4096 REF x 512 4096 Figure 5 18 12 Bit ADC0 Window Interrupt Example Left Justified Single Ended Data Given AMX0SL 0x00 AMX0CF 0x00 AD0LJST 1 ADC0LTH ADC0LTL 0x2000 ADC0GTH ADC0GTL 0x1000 An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt AD0WINT 1 if the resulting ADC0 Data Word is 0x2000 and 0x1000 Given AMX0SL 0x00 ...

Page 65: ...age AD0 0 AD0 1 REF x 2047 2048 REF x 256 2048 REF x 1 2048 Figure 5 19 12 Bit ADC0 Window Interrupt Example Left Justified Differential Data Given AMX0SL 0x00 AMX0CF 0x01 AD0LJST 1 ADC0LTH ADC0LTL 0x1000 ADC0GTH ADC0GTL 0xFFF0 An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt AD0WINT 1 if the resulting ADC0 Data Word is 0x1000 and 0xFFF0 Two s complement math Given AMX0SL 0x00...

Page 66: ...stortion 66 dB Total Harmonic Distortion Up to the 5th harmonic 75 dB Spurious Free Dynamic Range 80 dB CONVERSION RATE SAR Clock Frequency 2 5 MHz Conversion Time in SAR Clocks 16 clocks Track Hold Acquisition Time 1 5 µs Throughput Rate 100 ksps ANALOG INPUTS Input Voltage Range Single ended operation 0 VREF V Common mode Voltage Range Differential operation AGND AV V Input Capacitance 10 pF TEM...

Page 67: ...sfer function is shown in Figure 6 2 AMUX input pairs can be programmed to operate in either differential or single ended mode This allows the user to select the best measure ment technique for each input channel and even accommodates mode changes on the fly The AMUX defaults to all single ended inputs upon reset There are two registers associated with the AMUX the Channel Selection register AMX0S...

Page 68: ...PGA input when the Temperature Sensor is selected by bits AMX0AD3 0 in register AMX0SL this voltage will be amplified by the PGA according to the user programmed PGA settings 0 50 50 100 Celsius 0 500 0 600 0 700 0 800 0 900 Volts VTEMP 0 00286 TEMPC 0 776 for PGA Gain 1 1 000 Figure 6 2 Typical Temperature Sensor Transfer Function ...

Page 69: ...on is complete The fall ing edge of AD0BUSY triggers an interrupt when enabled and sets the AD0INT interrupt flag ADC0CN 5 Con verted data is available in the ADC0 data word MSB and LSB registers ADC0H ADC0L Converted data can be either left or right justified in the ADC0H ADC0L register pair see example in Figure 6 11 depending on the pro grammed state of the AD0LJST bit in the ADC0CN register Wh...

Page 70: ...n when the entire chip is in low power standby or sleep modes Low power track and hold mode is also useful when AMUX or PGA settings are frequently changed to ensure that settling time requirements are met see Section 6 2 3 Settling Time Requirements on page 71 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CNVSTR0 AD0CM 1 0 10 ADC0TM 1 ADC0TM 0 Timer 2 Timer 3 Overflow Write 1 to AD0BUSY AD0CM 1 0 00 01 ...

Page 71: ... Temperature Sensor output RTOTAL reduces to RMUX An absolute minimum settling time of 1 5 µs is required after any MUX or PGA selection Note that in low power tracking mode three SAR clocks are used for tracking at the start of every conversion For most applications these three SAR clocks will meet the tracking requirements Where SA is the settling accuracy given as a fraction of an LSB for examp...

Page 72: ...are respectively differential input pair Bit1 AIN23IC AIN0 2 AIN0 3 Input Pair Configuration Bit 0 AIN0 2 and AIN0 3 are independent single ended inputs 1 AIN0 2 AIN0 3 are respectively differential input pair Bit0 AIN01IC AIN0 0 AIN0 1 Input Pair Configuration Bit 0 AIN0 0 and AIN0 1 are independent single ended inputs 1 AIN0 0 AIN0 1 are respectively differential input pair NOTE The ADC0 Data Wo...

Page 73: ...AIN0 6 AIN0 7 TEMP SENSOR 0100 AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 TEMP SENSOR 0101 AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 TEMP SENSOR 0110 AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 TEMP SENSOR 0111 AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 TEMP SENSOR 1000 AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 TEMP SENSOR 1001 AIN0...

Page 74: ...version Clock should be less than or equal to 2 5 MHz When the AD0SC bits are equal to 00000b the SAR Conversion clock is equal to SYSCLK to facili tate faster ADC conversions at slower SYSCLK speeds Bits2 0 AMP0GN2 0 ADC0 Internal Amplifier Gain PGA 000 Gain 1 001 Gain 2 010 Gain 4 011 Gain 8 10x Gain 16 11x Gain 0 5 SFR Page SFR Address 0 0xBC R W R W R W R W R W R W R W R W Reset Value AD0SC4 A...

Page 75: ... of 1 to AD0BUSY 01 ADC0 conversion initiated on overflow of Timer 3 10 ADC0 conversion initiated on rising edge of external CNVSTR0 11 ADC0 conversion initiated on overflow of Timer 2 If AD0TM 1 00 Tracking starts with the write of 1 to AD0BUSY and lasts for 3 SAR clocks followed by con version 01 Tracking started by the overflow of Timer 3 and lasts for 3 SAR clocks followed by conversion 10 ADC...

Page 76: ...ata Word SFR Page SFR Address 0 0xBF R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Figure 6 10 ADC0L ADC0 Data Word LSB Register Bits7 0 ADC0 Data Word Low Order Bits For AD0LJST 0 Bits 7 0 are the lower 8 bits of the 10 bit ADC0 Data Word For AD0LJST 1 Bits 7 4 are the lower 4 bits of the 10 bit ADC0 Data Word Bits3 0 will always read 0 SFR Page SFR ...

Page 77: ...X0CF 0x00 AMX0SL 0x00 Example ADC0 Data Word Conversion Map AIN0 0 AIN0 1 Differential Input Pair AMX0CF 0x01 AMX0SL 0x00 For AD0LJST 0 n 10 for Single Ended n 9 for Differential AIN0 0 AGND Volts ADC0H ADC0L AD0LJST 0 ADC0H ADC0L AD0LJST 1 VREF 1023 1024 0x03FF 0xFFC0 VREF 2 0x0800 0x8000 VREF 511 1024 0x01FF 0x7FC0 0 0x0000 0x0000 AIN0 0 AIN0 1 Volts ADC0H ADC0L AD0LJST 0 ADC0H ADC0L AD0LJST 1 V...

Page 78: ...0 Less Than registers ADC0GTH ADC0GTL ADC0LTH and ADC0LTL Reference comparisons are shown starting on page 80 Notice that the window detector flag can be asserted when the measured data is inside or outside the user programmed limits depending on the programming of the ADC0GTx and ADC0LTx registers Figure 6 12 ADC0GTH ADC0 Greater Than Data High Byte Register Bits7 0 High byte of ADC0 Greater Than...

Page 79: ...Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Figure 6 14 ADC0LTH ADC0 Less Than Data High Byte Register Figure 6 15 ADC0LTL ADC0 Less Than Data Low Byte Register Bits7 0 Low byte of ADC0 Less Than Data Word SFR Page SFR Address 0 0xC6 R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ...

Page 80: ...0100 ADC0GTH ADC0GTL 0x0200 An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt AD0WINT 1 if the resulting ADC0 Data Word is 0x0200 or 0x0100 0x03FF 0x0201 0x0200 0x01FF 0x0101 0x0100 0x00FF 0x0000 ADWINT 1 ADWINT not affected ADWINT not affected ADC Data Word 0x03FF 0x0201 0x0200 0x01FF 0x0101 0x0100 0x00FF 0x0000 ADWINT 1 ADWINT not affected ADWINT 1 ADC0LTH ADC0LTL ADC0GTH ADC...

Page 81: ...REF x 511 512 REF x 256 512 REF x 1 512 Figure 6 17 10 Bit ADC0 Window Interrupt Example Right Justified Differential Data Given AMX0SL 0x00 AMX0CF 0x01 AD0LJST 0 ADC0LTH ADC0LTL 0x0100 ADC0GTH ADC0GTL 0xFFFF An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt AD0WINT 1 if the resulting ADC0 Data Word is 0x0100 and 0xFFFF In two s complement math 0xFFFF 1 Given AMX0SL 0x00 AMX0CF...

Page 82: ...1024 0 Input Voltage AD0 0 AGND REF x 1023 1024 REF x 256 1024 REF x 512 1024 Figure 6 18 10 Bit ADC0 Window Interrupt Example Left Justified Single Ended Data Given AMX0SL 0x00 AMX0CF 0x00 AD0LJST 1 ADC0LTH ADC0LTL 0x2000 ADC0GTH ADC0GTL 0x1000 An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt AD0WINT 1 if the resulting ADC0 Data Word is 0x2000 and 0x1000 Given AMX0SL 0x00 AMX...

Page 83: ... AD0 0 AD0 1 REF x 511 512 REF x 128 512 REF x 1 512 Figure 6 19 10 Bit ADC0 Window Interrupt Example Left Justified Differential Data Given AMX0SL 0x00 AMX0CF 0x01 AD0LJST 1 ADC0LTH ADC0LTL 0x2000 ADC0GTH ADC0GTL 0xFFC0 An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt AD0WINT 1 if the resulting ADC0 Data Word is 0x2000 and 0xFFC0 Two s complement math Given AMX0SL 0x00 AMX0CF...

Page 84: ...Distortion 59 dB Total Harmonic Distortion Up to the 5th harmonic 70 dB Spurious Free Dynamic Range 80 dB CONVERSION RATE SAR Clock Frequency 2 5 MHz Conversion Time in SAR Clocks 16 clocks Track Hold Acquisition Time 1 5 µs Throughput Rate 100 ksps ANALOG INPUTS Input Voltage Range Single ended operation 0 VREF V Common mode Voltage Range Differential operation AGND AV V Input Capacitance 10 pF T...

Page 85: ...5 The PGA amplifies the ADC2 output signal by an amount determined by the states of the AMP2GN2 0 bits in the ADC2 Con figuration register ADC2CF Figure 7 6 The PGA can be software programmed for gains of 0 5 1 2 or 4 Gain defaults to 0 5 on reset Important Note AIN2 pins also function as Port 1 I O pins and must be configured as analog inputs when used as ADC2 inputs To configure an AIN2 pin for ...

Page 86: ...1 to AD2BUSY it is recommended to poll AD2INT to determine when the conversion is complete The recommended procedure is Step 1 Write a 0 to AD2INT Step 2 Write a 1 to AD2BUSY Step 3 Poll AD2INT for 1 Step 4 Process ADC2 data When CNVSTR2 is used as a conversion start source it must be enabled in the crossbar and the corresponding pin must be set to open drain high impedance mode see Section 19 POR...

Page 87: ...TM 1 AD2TM 0 SAR Clocks 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 SAR Clocks Track Convert Low Power Mode Low Power or Convert Track or Convert Convert Track B ADC Timing for Internal Trigger Source 1 2 3 4 5 6 7 8 9 CNVSTR2 AD2CM 2 0 010 AD2TM 1 A ADC Timing for External Trigger Source SAR Clocks Track or Convert Convert Track AD2TM 0 Track Convert Low Power Mode Low Power or Convert ...

Page 88: ...MUX selection Note that in low power tracking mode three SAR2 clocks are used for tracking at the start of every conversion For most applications these three SAR2 clocks will meet the tracking requirements Where SA is the settling accuracy given as a fraction of an LSB for example 0 25 to settle within 1 4 LSB t is the required settling time in seconds RTOTAL is the sum of the ADC2 MUX resistance ...

Page 89: ...are respectively differential input pair Bit1 PIN23IC AIN2 2 AIN2 3 Input Pair Configuration Bit 0 AIN2 2 and AIN2 3 are independent single ended inputs 1 AIN2 2 and AIN2 3 are respectively differential input pair Bit0 PIN01IC AIN2 0 AIN2 1 Input Pair Configuration Bit 0 AIN2 0 and AIN2 1 are independent single ended inputs 1 AIN2 0 and AIN2 1 are respectively differential input pair NOTE The ADC2...

Page 90: ...7 0011 AIN2 0 AIN2 1 AIN2 2 AIN2 3 AIN2 4 AIN2 5 AIN2 6 AIN2 7 0100 AIN2 0 AIN2 1 AIN2 2 AIN2 3 AIN2 4 AIN2 5 AIN2 6 AIN2 7 0101 AIN2 0 AIN2 1 AIN2 2 AIN2 3 AIN2 4 AIN2 5 AIN2 6 AIN2 7 0110 AIN2 0 AIN2 1 AIN2 2 AIN2 3 AIN2 4 AIN2 5 AIN2 6 AIN2 7 0111 AIN2 0 AIN2 1 AIN2 2 AIN2 3 AIN2 4 AIN2 5 AIN2 6 AIN2 7 1000 AIN2 0 AIN2 1 AIN2 2 AIN2 3 AIN2 4 AIN2 5 AIN2 6 AIN2 7 1001 AIN2 0 AIN2 1 AIN2 2 AIN2 3...

Page 91: ... AD2SC4 0 and CLKSAR2 refers to the desired ADC2 SAR clock Note the ADC2 SAR Conversion Clock should be less than or equal to 7 5 MHz Bit2 UNUSED Read 0b Write don t care Bits1 0 AMP2GN1 0 ADC2 Internal Amplifier Gain PGA 00 Gain 0 5 01 Gain 1 10 Gain 2 11 Gain 4 SFR Page SFR Address 2 0xBC R W R W R W R W R W R W R W R W Reset Value AD2SC4 AD2SC3 AD2SC2 AD2SC1 AD2SC0 AMP2GN1 AMP2GN0 11111000 Bit7...

Page 92: ...of 1 to AD2BUSY 001 ADC2 conversion initiated on overflow of Timer 3 010 ADC2 conversion initiated on rising edge of external CNVSTR2 011 ADC2 conversion initiated on overflow of Timer 2 1xx ADC2 conversion initiated on write of 1 to AD0BUSY synchronized with ADC0 software commanded conversions AD2TM 1 000 Tracking initiated on write of 1 to AD2BUSY and lasts 3 SAR2 clocks followed by conver sion ...

Page 93: ...ter as follows Example ADC2 Data Word Conversion Map Single Ended AIN2 0 Input AMX2CF 0x00 AMX2SL 0x00 Differential Example 8 bit ADC Data Word appears in the ADC2 Data Word Register as follows Example ADC2 Data Word Conversion Map Differential AIN2 0 AIN2 1 Input AMX2CF 0x01 AMX2SL 0x00 AIN2 0 AGND Volts ADC2 VREF 255 256 0xFF VREF 128 256 0x80 VREF 64 256 0x40 0 0x00 AIN2 0 AIN2 1 Volts ADC2 VRE...

Page 94: ...he con tents of the ADC2LT and ADC2GT registers 7 3 1 Window Detector In Single Ended Mode Figure 7 10 shows two example window comparisons for Single ended mode with ADC2LT 0x20 and ADC2GT 0x10 Notice that in Single ended mode the codes vary from 0 to VREF 255 256 and are represented as 8 bit unsigned integers In the left example an AD2WINT interrupt will be generated if the ADC2 conversion word ...

Page 95: ...ADC2LT if 0xFF 1d ADC2 0x0F 16d In the right example an AD2WINT interrupt will be generated if ADC2 is outside of the range defined by ADC2GT and ADC2LT if ADC2 0xFF 1d or ADC2 0x10 16d Figure 7 11 ADC2 Window Compare Examples Differential Mode 0x7F 127d 0x11 17d 0x10 16d 0x0F 15d 0x00 0d 0xFF 1d 0xFE 2d 0x80 128d REF Input Voltage AIN2 x AIN2 y REF x 127 128 REF x 16 128 REF x 1 256 0x7F 127d 0x1...

Page 96: ... SFR Page SFR Address 2 0xC4 R W R W R W R W R W R W R W R W Reset Value 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Figure 7 13 ADC2LT ADC2 Less Than Data Byte Register Bits7 0 ADC2 Less Than Data Word SFR Page SFR Address 2 0xC6 R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ...

Page 97: ...SB Offset Temperature Coefficient TBD ppm C DYNAMIC PERFORMANCE 10 kHz sine wave input 1 dB below Full Scale 500 ksps Signal to Noise Plus Distortion TBD 47 dB Total Harmonic Distortion Up to the 5th harmonic 51 dB Spurious Free Dynamic Range 52 dB CONVERSION RATE SAR Clock Frequency 7 5 MHz Conversion Time in SAR Clocks 8 clocks Track Hold Acquisition Time 800 ns Throughput Rate 500 ksps ANALOG I...

Page 98: ...C8051F120 1 2 3 4 5 6 7 98 Rev 1 2 ...

Page 99: ...109 for more information on configuring the voltage reference for the DACs 8 1 DAC Output Scheduling Each DAC features a flexible output update mechanism which allows for seamless full scale changes and supports jitter free updates for waveform generation The following examples are written in terms of DAC0 but DAC1 opera tion is identical 8 1 1 Update Output On Demand In its default mode DAC0CN 4 ...

Page 100: ...tput When the DAC0MD bits DAC0CN 4 3 are set to 01 10 or 11 writes to both DAC data registers DAC0L and DAC0H are held until an associated Timer overflow event Timer 3 Timer 4 or Timer 2 respectively occurs at which time the DAC0H DAC0L contents are copied to the DAC input latches allowing the DAC output to change to the new value 8 2 DAC Output Scaling Justification In some instances input data s...

Page 101: ...W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0xD3 0 Figure 8 3 DAC0L DAC0 Low Byte Register Bits7 0 DAC0 Data Word Least Significant Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0xD2 0 ...

Page 102: ... DAC0H 3 0 while the least significant byte is in DAC0L 001 The most significant 5 bits of the DAC0 Data Word is in DAC0H 4 0 while the least significant 7 bits are in DAC0L 7 1 010 The most significant 6 bits of the DAC0 Data Word is in DAC0H 5 0 while the least significant 6 bits are in DAC0L 7 2 011 The most significant 7 bits of the DAC0 Data Word is in DAC0H 6 0 while the least significant 5 ...

Page 103: ...W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0xD3 1 Figure 8 6 DAC1L DAC1 Low Byte Register Bits7 0 DAC1 Data Word Least Significant Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0xD2 1 ...

Page 104: ...DAC1H 3 0 while the least significant byte is in DAC1L 001 The most significant 5 bits of the DAC1 Data Word is in DAC1H 4 0 while the least significant 7 bits are in DAC1L 7 1 010 The most significant 6 bits of the DAC1 Data Word is in DAC1H 5 0 while the least significant 6 bits are in DAC1L 7 2 011 The most significant 7 bits of the DAC1 Data Word is in DAC1H 6 0 while the least significant 5 b...

Page 105: ...4 3 30 mV Offset Tempco 6 ppm C Gain Error 20 60 mV Gain Error Tempco 10 ppm C VDD Power Supply Rejection Ratio 60 dB Output Impedance in Shutdown Mode DACnEN 0 100 kΩ Output Sink Current 300 µA Output Short Circuit Current Data Word 0xFFF 15 mA DYNAMIC PERFORMANCE Voltage Output Slew Rate Load 40pF 0 44 V µs Output Settling Time to 1 2 LSB Load 40pF Output swing from code 0xFFF to 0x014 10 µs Out...

Page 106: ...C8051F120 1 2 3 4 5 6 7 106 Rev 1 2 Notes ...

Page 107: ...for ADC0 and ADC2 The BIASE bit in REF0CN enables the on board reference generator while the REFBE bit enables the gain of two buffer amplifier which drives the VREF pin When disabled the supply current drawn by the bandgap and buffer amplifier falls to less than 1 µA typical and the output of the buffer amplifier enters a high impedance state If the internal bandgap is used as the reference volta...

Page 108: ... 7µF tantalum 0 1µF ceramic bypass 2 ms VREF Turn on Time 2 0 1µF ceramic bypass 20 µs VREF Turn on Time 3 no bypass cap 10 µs EXTERNAL REFERENCE REFBE 0 Input Voltage Range 1 00 AV 0 3 V Input Current 0 1 µA Figure 9 2 REF0CN Reference Control Register Bits7 5 UNUSED Read 000b Write don t care Bit4 AD0VRS ADC0 Voltage Reference Select 0 ADC0 voltage reference from VREF0 pin 1 ADC0 voltage referen...

Page 109: ... bit enables the gain of two buffer amplifier which drives the VREF pin When disabled the supply current drawn by the bandgap and buffer amplifier falls to less than 1 µA typical and the output of the buffer amplifier enters a high impedance state If the internal bandgap is used as the reference voltage generator BIASE and REFBE must both be set to 1 this includes any time a DAC is used If the int...

Page 110: ... 7µF tantalum 0 1µF ceramic bypass 2 ms VREF Turn on Time 2 0 1µF ceramic bypass 20 µs VREF Turn on Time 3 no bypass cap 10 µs EXTERNAL REFERENCE REFBE 0 Input Voltage Range 1 00 AV 0 3 V Input Current 0 1 µA Figure 10 2 REF0CN Reference Control Register Bits7 5 UNUSED Read 000b Write don t care Bit4 AD0VRS ADC0 Voltage Reference Select 0 ADC0 voltage reference from VREFA pin 1 ADC0 voltage refere...

Page 111: ...ain or push pull modes See Section 19 1 Ports 0 through 3 and the Priority Crossbar Decoder on page 217 for Crossbar and port initialization details Figure 11 1 Comparator Functional Block Diagram Q Q SET CLR D Q Q SET CLR D Crossbar Interrupt Handler Reset Decision Tree SYNCHRONIZER CP0 CP0 AGND CPT0CN CP0HYN0 CP0MD CP0HYN1 CP0HYP0 CP0HYP1 CP0FIF CP0RIF CP0OUT CP0EN AV CPT0MD CP0MD0 CP0MD1 CP0FIE...

Page 112: ...he hysteresis of each comparator is software programmable via its respective Comparator control register CPT0CN and CPT1CN for Comparator0 and Comparator1 respectively The user can program both the amount of hysteresis voltage referred to the input voltage and the positive and negative going symmetry of this hysteresis around the threshold voltage The output of the comparator can be polled in soft...

Page 113: ...Bits Negative Hysteresis Voltage Programmed by CP0HYN Bits VIN VIN INPUTS CIRCUIT CONFIGURATION _ CP0 CP0 CP0 VIN VIN OUT VOH Positive Hysteresis Disabled Maximum Positive Hysteresis Negative Hysteresis Disabled Maximum Negative Hysteresis OUTPUT VOL Figure 11 2 Comparator Hysteresis Plot ...

Page 114: ...omparator0 Falling Edge has occurred since this flag was last cleared 1 Comparator0 Falling Edge has occurred Bits3 2 CP0HYP1 0 Comparator0 Positive Hysteresis Control Bits 00 Positive Hysteresis Disabled 01 Positive Hysteresis 5 mV 10 Positive Hysteresis 10 mV 11 Positive Hysteresis 15 mV Bits1 0 CP0HYN1 0 Comparator0 Negative Hysteresis Control Bits 00 Negative Hysteresis Disabled 01 Negative Hy...

Page 115: ...Falling Edge Interrupt Enable Bit 0 Comparator 0 falling edge interrupt disabled 1 Comparator 0 falling edge interrupt enabled Bits3 2 UNUSED Read 00b Write don t care Bits1 0 CP0MD1 CP0MD0 Comparator0 Mode Select These bits select the response time for Comparator0 SFR Page SFR Address 1 0x89 R W R W R W R W R W R W R W R W Reset Value CP0RIE CP0FIE CP0MD1 CP0MD0 00000010 Bit7 Bit6 Bit5 Bit4 Bit3 ...

Page 116: ...ator1 Falling Edge has occurred since this flag was last cleared 1 Comparator1 Falling Edge Interrupt has occurred Bits3 2 CP1HYP1 0 Comparator1 Positive Hysteresis Control Bits 00 Positive Hysteresis Disabled 01 Positive Hysteresis 5 mV 10 Positive Hysteresis 10 mV 11 Positive Hysteresis 15 mV Bits1 0 CP1HYN1 0 Comparator1 Negative Hysteresis Control Bits 00 Negative Hysteresis Disabled 01 Negati...

Page 117: ...Falling Edge Interrupt Enable Bit 0 Comparator 1 falling edge interrupt disabled 1 Comparator 1 falling edge interrupt enabled Bits3 2 UNUSED Read 00b Write don t care Bits1 0 CP1MD1 CP1MD0 Comparator1 Mode Select These bits select the response time for Comparator1 SFR Page SFR Address 2 0x89 R W R W R W R W R W R W R W R W Reset Value CP1RIE CP1FIE CP1MD1 CP1MD0 00000010 Bit7 Bit6 Bit5 Bit4 Bit3 ...

Page 118: ...0 ns Common Mode Rejection Ratio 1 5 4 mV V Positive Hysteresis 1 CPnHYP1 0 00 0 1 mV Positive Hysteresis 2 CPnHYP1 0 01 2 4 5 7 mV Positive Hysteresis 3 CPnHYP1 0 10 4 9 13 mV Positive Hysteresis 4 CPnHYP1 0 11 10 17 25 mV Negative Hysteresis 1 CPnHYN1 0 00 0 1 mV Negative Hysteresis 2 CPnHYN1 0 01 2 4 5 7 mV Negative Hysteresis 3 CPnHYN1 0 10 4 9 13 mV Negative Hysteresis 4 CPnHYN1 0 11 10 17 25...

Page 119: ...gle integrated circuit The CIP 51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability see Figure 12 1 for a block diagram The CIP 51 includes the following features Figure 12 1 CIP 51 Block Diagram DATA BUS TMP1 TMP2 PRGM ADDRESS REG PC INCREMENTER ALU PSW DATA BUS DATA BUS MEMORY INTERFACE M...

Page 120: ...lopment environment IDE including editor macro assembler debugger and programmer The IDE s debugger and programmer interface to the CIP 51 via its JTAG interface to provide fast and efficient in system device programming and debugging Third party macro assemblers and C compilers are also available 12 1 Instruction Set The instruction set of the CIP 51 System Controller is fully compatible with the...

Page 121: ...t RAM from A with borrow 1 2 SUBB A data Subtract immediate from A with borrow 2 2 INC A Increment A 1 1 INC Rn Increment register 1 1 INC direct Increment direct byte 2 2 INC Ri Increment indirect RAM 1 2 DEC A Decrement A 1 1 DEC Rn Decrement register 1 1 DEC direct Decrement direct byte 2 2 DEC Ri Decrement indirect RAM 1 2 INC DPTR Increment Data Pointer 1 1 MUL AB Multiply A and B 1 4 DIV AB ...

Page 122: ... MOV direct data Move immediate to direct byte 3 3 MOV Ri A Move A to indirect RAM 1 2 MOV Ri direct Move direct byte to indirect RAM 2 2 MOV Ri data Move immediate to indirect RAM 2 2 MOV DPTR data16 Load DPTR with 16 bit constant 3 3 MOVC A A DPTR Move code byte relative DPTR to A 1 3 MOVC A A PC Move code byte relative PC to A 1 3 MOVX A Ri Move external data 8 bit address to A 1 3 MOVX Ri A Mo...

Page 123: ...Long subroutine call 3 4 RET Return from subroutine 1 5 RETI Return from interrupt 1 5 AJMP addr11 Absolute jump 2 3 LJMP addr16 Long jump 3 4 SJMP rel Short jump relative address 2 3 JMP A DPTR Jump indirect relative to DPTR 1 3 JZ rel Jump if A equals zero 2 2 3 JNZ rel Jump if A does not equal zero 2 2 3 CJNE A direct rel Compare direct byte to A and jump if not equal 3 3 4 CJNE A data rel Comp...

Page 124: ...his could be a direct access Data RAM location 0x00 0x7F or an SFR 0x80 0xFF data 8 bit constant data16 16 bit constant bit Direct accessed bit in Data RAM or SFR addr11 11 bit destination address used by ACALL and AJMP The destination must be within the same 2K byte page of program memory as the first byte of the following instruction addr16 16 bit destination address used by LCALL and LJMP The d...

Page 125: ... code execution while the COBANK bits select the bank to be used for direct writes and reads of the FLASH memory Note 1024 bytes of the memory in Bank 3 0x1FC00 to 0x1FFFF are reserved and are not available for user program or data storage Program memory is normally assumed to be read only However the CIP 51 can write to program memory by setting the Program Store Write Enable bit PSCTL 0 and usin...

Page 126: ...Target Bank 3 Bits 3 2 Reserved Bits 1 0 IFBANK Instruction Fetch Operations Bank Select These bits select which FLASH bank is used for instruction fetches involving addresses 0x8000 to 0xFFFF These bits can only be changed from code in Bank 0 see Figure 12 4 00 Instructions Fetch From Bank 0 note that Bank 0 is also mapped between 0x0000 to 0x7FFF 01 Instructions Fetch From Bank 1 10 Instructions...

Page 127: ...it Addressable Locations In addition to direct access to data memory organized as bytes the sixteen data memory locations at 0x20 through 0x2F are also accessible as 128 individually addressable bits Each bit has a bit address from 0x00 to 0x7F Bit 0 of the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address 0x07 Bit 7 of the byte at 0x2F has bit address 0x7F A bit ac...

Page 128: ...gure 12 12 The procedure for reading and writing an SFR is as follows 1 Select the appropriate SFR page number using the SFRPAGE register 2 Use direct accessing mode to read or write the special function register MOV instruction 12 2 6 2 Interrupts and SFR Paging When an interrupt occurs the SFR Page Register will automatically switch to the SFR page containing the flag bit that caused the interru...

Page 129: ...of the SFR locations address and SFR page is provided in Table 12 2 in the form of an SFR memory map Each memory location in the map has an SFR page row denoting the page in which that SFR resides Note that certain SFR s are accessible from ALL SFR pages and are denoted by the ALL PAGES designation For exam ple the Port I O registers P0 P1 P2 and P3 all have the ALL PAGES designation indicating th...

Page 130: ...nter Array PCA and the 10 bit ADC ADC2 window comparator to monitor a voltage The PCA is timing a critical control function in its interrupt service routine ISR so its interrupt is enabled and is set to high priority The ADC2 is monitoring a voltage that is less important but to minimize the soft ware overhead its window comparator is being used with an associated ISR that is set to low priority A...

Page 131: ...omatically placed in the SFRPAGE register SFR Page 0x02 SFRPAGE is considered the top of the SFR Page Stack Soft ware can now access the ADC2 SFR s Software may switch to any SFR Page by writing a new value to the SFRPAGE register at any time during the ADC2 ISR to access SFR s that are not on SFR Page 0x02 See Figure 12 7 below 0x02 ADC2 0x0F Port 5 SFRPAGE SFRLAST SFRNEXT SFRPAGE pushed to SFRNE...

Page 132: ...FRPAGE register before the PCA interrupt SFR Page 2 for ADC2 is pushed down the stack into SFRNEXT Likewise the value that was in the SFRNEXT register before the PCA interrupt in this case SFR Page 0x0F for Port 5 is pushed down to the SFR LAST register the bottom of the stack Note that a value stored in SFRLAST via a previous software write to the SFRLAST register will be overwritten See Figure 1...

Page 133: ... the SFRPAGE register Software in the ADC2 ISR can continue to access SFR s as it did prior to the PCA interrupt Likewise the contents of SFR LAST are moved to the SFRNEXT register Recall this was the SFR Page value 0x0F being used to access Port 5 before the ADC2 interrupt occurred See Figure 12 9 below 0x02 ADC2 0x0F Port 5 SFRPAGE SFRLAST SFRNEXT SFR Page 0x00 Automatically popped off of the st...

Page 134: ...ected prior to the interrupt call Direct access to the SFR Page stack can be useful to enable real time operating systems to control and manage context switching between multiple tasks Push operations on the SFR Page Stack only occur on interrupt service and pop operations only occur on interrupt exit execution on the RETI instruction The automatic switching of the SFRPAGE and operation of the SFR...

Page 135: ...terrupt R W R W R W R W R W R W R W R W Reset Value SFRPGEN 00000001 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0x96 F Figure 12 12 SFRPAGE SFR Page Register Bits7 0 SFR Page Bits Byte Represents the SFR Page the C8051 MCU uses when reading or modifying SFR s Write Sets the SFR Page Read Byte is the SFR page the C8051 MCU is using When enabled in the SFR Page Control Register SFR...

Page 136: ... register upon a return from interrupt R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0x85 All Pages Figure 12 14 SFRLAST SFR Last Register Bits7 0 SFR Page Stack Bits SFR page context is retained upon interrupts return from interrupts in a 3 byte SFR Page Stack SFRPAGE is the first entry SFRNEXT is the second and SFRLAST is the th...

Page 137: ...0 PCA0CPH5 XBR1 XBR2 EIE1 ALL PAGES EIE2 ALL PAGES D8 0 1 2 3 F PCA0CN P5 PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4 PCA0CPM5 D0 0 1 2 3 F PSW ALL PAGES REF0CN DAC0L DAC1L DAC0H DAC1H DAC0CN DAC1CN C8 0 1 2 3 F TMR2CN TMR3CN TMR4CN P4 TMR2CF TMR3CF TMR4CF RCAP2L RCAP3L RCAP4L RCAP2H RCAP3H RCAP4H TMR2L TMR3L TMR4L TMR2H TMR3H TMR4H SMB0CR C0 0 1 2 3 F SMB0CN MAC0STA SMB0STA MAC0AL SMB0DAT...

Page 138: ...L0 OSCICN TL1 OSCICL TH0 OSCXCN TH1 PLL0DIV CKCON PLL0MUL PSCTL PLL0FLT 80 0 1 2 3 F P0 ALL PAGES SP ALL PAGES DPL ALL PAGES DPH ALL PAGES SFRPAGE ALL PAGES SFRNEXT ALL PAGES SFRLAST ALL PAGES PCON ALL PAGES Table 12 3 Special Function Registers SFRs are listed in alphabetical order All undefined SFR locations are reserved Register Address SFR Page Description Page No ACC 0xE0 All Pages Accumulato...

Page 139: ...114 CPT0MD 0x89 1 Comparator 0 Configuration page 115 CPT1CN 0x88 2 Comparator 1 Control page 116 CPT1MD 0x89 2 Comparator 1 Configuration page 117 DAC0CN 0xD4 0 DAC0 Control page 102 DAC0H 0xD3 0 DAC0 High Byte page 101 DAC0L 0xD2 0 DAC0 Low Byte page 101 DAC1CN 0xD4 1 DAC1 Control page 104 DAC1H 0xD3 1 DAC1 High Byte page 103 DAC1L 0xD2 1 DAC1 Low Byte page 103 DPH 0x83 All Pages Data Pointer Hi...

Page 140: ... F Port 2 Output Mode Configuration page 230 P3 0xB0 All Pages Port 3 Latch page 230 P3MDOUT 0xA7 F Port 3 Output Mode Configuration page 231 P4 0xC8 F Port 4 Latch page 233 P4MDOUT 0x9C F Port 4 Output Mode Configuration page 233 P5 0xD8 F Port 5 Latch page 234 P5MDOUT 0x9D F Port 5 Output Mode Configuration page 234 P6 0xE8 F Port 6 Latch page 235 P6MDOUT 0x9E F Port 6 Output Mode Configuration ...

Page 141: ... 0xCB 1 Timer 3 Capture Reload High Byte page 299 RCAP3L 0xCA 1 Timer 3 Capture Reload Low Byte page 299 RCAP4H 0xCB 2 Timer Counter 4 Capture Reload High Byte page 299 RCAP4L 0xCA 2 Timer Counter 4 Capture Reload Low Byte page 299 REF0CN 0xD1 0 Voltage Reference Control page 108 page 110 RSTSRC 0xEF 0 Reset Source page 171 SADDR0 0xA9 0 UART 0 Slave Address page 273 SADEN0 0xB9 0 UART 0 Slave Add...

Page 142: ...n page 298 TMR3CN 0xC8 1 Timer 3 Control page 298 TMR3H 0xCD 1 Timer 3 High Byte page 300 TMR3L 0xCC 1 Timer 3 Low Byte page 299 TMR4CF 0xC9 2 Timer Counter 4 Configuration page 298 TMR4CN 0xC8 2 Timer Counter 4 Control page 298 TMR4H 0xCD 2 Timer Counter 4 High Byte page 300 TMR4L 0xCC 2 Timer Counter 4 Low Byte page 299 WDTCN 0xFF All Pages Watchdog Timer Control page 170 XBR0 0xE1 F Port I O Cr...

Page 143: ...ncremented before every PUSH operation The SP register defaults to 0x07 after reset R W R W R W R W R W R W R W R W Reset Value 00000111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0x81 All Pages Figure 12 16 DPL Data Pointer Low Byte Bits7 0 DPL Data Pointer Low The DPL register is the low byte of the 16 bit DPTR DPTR is used to access indirectly addressed XRAM and FLASH memory R...

Page 144: ...gister accesses Bit2 OV Overflow Flag This bit is set to 1 under the following circumstances An ADD ADDC or SUBB instruction causes a sign change overflow A MUL instruction results in an overflow result is greater than 255 A DIV instruction causes a divide by zero condition The OV bit is cleared to 0 by the ADD ADDC SUBB MUL and DIV instructions in all other cases Bit1 F1 User Flag 1 This is a bit...

Page 145: ... ACC 2 ACC 1 ACC 0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address SFR Page 0xE0 All Pages Figure 12 20 B B Register Bits7 0 B B Register This register serves as a second accumulator for certain arithmetic operations R W R W R W R W R W R W R W R W Reset Value B 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address S...

Page 146: ...e CPU vectors to the ISR However most are not cleared by the hardware and must be cleared by software before returning from the ISR If an interrupt pending flag remains set after the CPU completes the return from interrupt RETI instruction a new interrupt request will be generated immediately and the CPU will re enter the ISR after the completion of the next instruction 12 7 1 MCU Interrupt Source...

Page 147: ...SMB0CN 3 Y ESMB0 EIE1 1 PSMB0 EIP1 1 ADC0 Window Comparator 0x0043 8 AD0WINT ADC0CN 1 Y EWADC0 EIE1 2 PWADC0 EIP1 2 PCA 0 0x004B 9 CF PCA0CN 7 CCFn PCA0CN n Y EPCA0 EIE1 3 PPCA0 EIP1 3 Comparator 0 Falling Edge 0x0053 10 CP0FIF CPT0CN 4 Y ECP0F EIE1 4 PCP0F EIP1 4 Comparator 0 Rising Edge 0x005B 11 CP0RIF CPT0CN 5 Y ECP0R EIE1 5 PCP0R EIP1 5 Comparator 1 Falling Edge 0x0063 12 CP1FIF CPT1CN 4 Y EC...

Page 148: ...n the interrupt occurs Pending interrupts are sampled and priority decoded each system clock cycle Therefore the fastest possible response time is 5 system clock cycles 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the ISR Additional clock cycles will be required if a cache miss occurs If an interrupt is pending when a RETI is executed a single instruction is ex...

Page 149: ...the masking of the Timer 2 interrupt 0 Disable Timer 2 interrupt 1 Enable Timer 2 interrupt Bit4 ES0 Enable UART0 Interrupt This bit sets the masking of the UART0 interrupt 0 Disable UART0 interrupt 1 Enable UART0 interrupt Bit3 ET1 Enable Timer 1 Interrupt This bit sets the masking of the Timer 1 interrupt 0 Disable Timer 1 interrupt 1 Enable Timer 1 interrupt Bit2 EX1 Enable External Interrupt 1...

Page 150: ...ority 1 Timer 1 interrupts set to high priority Bit2 PX1 External Interrupt 1 Priority Control This bit sets the priority of the External Interrupt 1 interrupt 0 External Interrupt 1 set to low priority 1 External Interrupt 1 set to high priority Bit1 PT0 Timer 0 Interrupt Priority Control This bit sets the priority of the Timer 0 interrupt 0 Timer 0 interrupt set to low priority 1 Timer 0 interru...

Page 151: ...lling edge interrupt 0 Disable CP0 falling edge interrupts 1 Enable CP0 falling edge interrupts Bit3 EPCA0 Enable Programmable Counter Array PCA0 Interrupt This bit sets the masking of the PCA0 interrupts 0 Disable PCA0 interrupts 1 Enable PCA0 interrupts Bit2 EWADC0 Enable Window Comparison ADC0 Interrupt This bit sets the masking of ADC0 Window Comparison interrupt 0 Disable ADC0 Window Comparis...

Page 152: ...g of ADC2 Window Comparison interrupt 0 Disable ADC2 Window Comparison Interrupts 1 Enable ADC2 Window Comparison Interrupts Bit2 ET4 Enable Timer 4 Interrupt This bit sets the masking of the Timer 4 interrupt 0 Disable Timer 4 interrupts 1 Enable Timer 4 interrupts Bit1 EADC0 Enable ADC0 End of Conversion Interrupt This bit sets the masking of the ADC0 End of Conversion Interrupt 0 Disable ADC0 E...

Page 153: ...priority 1 CP0 falling interrupt set to high priority Bit3 PPCA0 Programmable Counter Array PCA0 Interrupt Priority Control This bit sets the priority of the PCA0 interrupt 0 PCA0 interrupt set to low priority 1 PCA0 interrupt set to high priority Bit2 PWADC0 ADC0 Window Comparator Interrupt Priority Control This bit sets the priority of the ADC0 Window interrupt 0 ADC0 Window interrupt set to low...

Page 154: ...mpare interrupt 0 ADC2 Window Compare interrupt set to low priority 1 ADC2 Window Compare interrupt set to high priority Bit2 PT4 Timer 4 Interrupt Priority Control This bit sets the priority of the Timer 4 interrupt 0 Timer 4 interrupt set to low priority 1 Timer 4 interrupt set to high priority Bit1 PADC0 ADC0 End of Conversion Interrupt Priority Control This bit sets the priority of the ADC0 En...

Page 155: ... interrupt will cause the Idle Mode Selection bit PCON 0 to be cleared and the CPU to resume operation The pending interrupt will be serviced and the next instruction to be executed after the return from interrupt RETI will be the instruction immediately following the one that set the Idle Mode Select bit If Idle mode is terminated by an internal or external reset the CIP 51 performs a normal rese...

Page 156: ...d into power down mode Turns off oscillator Bit0 IDLE IDLE Mode Select Writing a 1 to this bit will place the CIP 51 into IDLE mode This bit will always read 0 1 CIP 51 forced into IDLE mode Shuts off clock to CPU but clock to Timers Interrupts and all peripherals remain active R W R W R W R W R W R W R W R W Reset Value STOP IDLE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Pa...

Page 157: ...ion and operation while the other eleven are used to store multi byte input and output data for MAC0 The Configuration register MAC0CF Figure 13 8 is used to configure and control MAC0 The Status reg ister MAC0STA Figure 13 9 contains flags to indicate overflow conditions as well as zero and negative results The 16 bit MAC0A MAC0AH MAC0AL and MAC0B MAC0BH MAC0BL registers are used as inputs to the...

Page 158: ...al point located between bits 31 and 30 Figure 13 3 shows how fractional numbers are stored in the SFRs 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 239 238 233 232 231 230 21 20 22 229 23 228 24 High Byte Low Byte MAC0OVR MAC0ACC3 MAC0ACC2 MAC0ACC1 MAC0ACC0 MAC0A and MAC0B Bit Weighting MAC0 Accumulator Bit Weighting Figure 13 2 Integer Mode Data Representation 1 2 1 2 2 2 3 2 4 2 5 2 6 ...

Page 159: ...perating in Multiply Only Mode MAC0 operates in Multiply Only mode when the MAC0MS bit MAC0CF 0 is set to 1 Multiply Only mode is identical to Multiply and Accumulate mode except that the multiplication result is added with a value of zero before being stored in the MAC0 accumulator i e it overwrites the current accumulator contents The result of the multipli cation is available in the MAC0 accumu...

Page 160: ...e examples for using MAC0 Figure 13 5 shows a series of two MAC operations using fractional numbers Figure 13 6 shows a single operation in Multiply Only mode with integer numbers The last example shown in Figure 13 7 demonstrates how the left shift and right shift operations can be used to modify the accumulator All of the examples assume that all of the flags in the MAC0STA register are initiall...

Page 161: ...lt NOP After this instruction the Rounding register is updated 4660 292 1360720 Figure 13 7 MAC0 Accumulator Shift Example The example below shifts the MAC0 accumulator left one bit and then right two bits MOV MAC0OVR 40h The next few instructions load the accumulator with the value MOV MAC0ACC3 88h 4088442211 Hex MOV MAC0ACC2 44h MOV MAC0ACC1 22h MOV MAC0ACC0 11h MOV MAC0CF 20h Initiate a Left sh...

Page 162: ...it will be cleared to 0 by hardware when the reset is complete Bit 2 MAC0SAT Saturate Rounding Register This bit controls whether the Rounding Register will saturate If this bit is set and a Soft Overflow occurs the Rounding Register will saturate This bit does not affect the operation of the MAC0 Accu mulator See Section 13 6 for more details about rounding and saturation 0 Rounding Register will...

Page 163: ...s bit is set to 1 when a MAC operation causes an overflow into the MAC0OVR register i e when the MAC0OVR register is not equal to 0x00 or 0xFF If the MAC0OVR register is equal to 0x00 or 0xFF after a MAC operation this bit is cleared to 0 Bit 0 MAC0N Negative Flag If the MAC Accumulator result is negative this bit will be set to 1 If the result is positive or zero this flag will be cleared to 0 No...

Page 164: ... Register Bits 7 0 Low Byte bits 7 0 of MAC0 B Register A write to this register initiates a Multiply or Multiply and Accumulate operation Note The contents of this register should not be changed by software during the first MAC0 pipeline stage R R R R R R R R Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x91 SFR Page 3 Figure 13 14 MAC0ACC3 MAC0 Accumulator Byte 3 Regi...

Page 165: ...line stages R R R R R R R R Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x94 SFR Page 3 Figure 13 17 MAC0ACC0 MAC0 Accumulator Byte 0 Register Bits 7 0 Byte 0 bits 7 0 of MAC0 Accumulator Note The contents of this register should not be changed by software during the first two MAC0 pipeline stages R R R R R R R R Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 ...

Page 166: ...unding Register R R R R R R R R Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xCF SFR Page 3 Figure 13 20 MAC0RNDL MAC0 Rounding Register Low Byte Bits 7 0 Low Byte bits 7 0 of MAC0 Rounding Register R R R R R R R R Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xCE SFR Page 3 ...

Page 167: ...om the reset state the program counter PC is reset and the system clock defaults to the internal oscillator running at its lowest frequency Refer to Section 15 OSCILLATORS on page 173 for information on selecting and configuring the system clock source The Watchdog Timer is enabled using its longest timeout interval see Sec tion 14 7 Watchdog Timer Reset on page 169 Once the system clock source is...

Page 168: ...n reset 14 2 Power fail Reset When a power down transition or power irregularity causes VDD to drop below VRST the power supply monitor will drive the RST pin low and return the CIP 51 to the reset state When VDD returns to a level above VRST the CIP 51 will leave the reset state in the same manner as that for the power on reset see Figure 14 2 Note that even though internal data memory contents a...

Page 169: ...d enabled before the CNVRSEF is set When configured as a reset CNVSTR0 is active low and level sensitive CNVSTR0 cannot be used to start ADC0 conversions when it is configured as a reset source After a CNVSTR0 reset the CNVRSEF flag RSTSRC 6 will read 1 signifying CNVSTR0 as the reset source otherwise this bit reads 0 The state of the RST pin is unaffected by this reset 14 7 Watchdog Timer Reset T...

Page 170: ... the initialization code 14 7 4 Setting WDT Interval WDTCN 2 0 control the watchdog timeout interval The interval is given by the following equation where Tsysclk is the system clock period For a 3 MHz system clock this provides an interval range of 0 021 ms to 349 5 ms WDTCN 7 must be logic 0 when setting this interval Reading WDTCN returns the programmed interval WDTCN 2 0 reads 111b after a sys...

Page 171: ...t 1 Source of last reset was a Missing Clock Detector timeout Bit1 PORSF Power On Reset Flag Write If the VDD monitor circuitry is enabled by tying the MONEN pin to a logic high state this bit can be written to select or de select the VDD monitor as a reset source 0 De select the VDD monitor as a reset source 1 Select the VDD monitor as a reset source Important At power on the VDD monitor is enabl...

Page 172: ... High Voltage 0 7 x VDD V RST Input Low Voltage 0 3 x VDD RST Input Leakage Current RST 0 0 V 50 µA VDD for RST Output Valid 1 0 V AV for RST Output Valid 1 0 V VDD POR Threshold VRST 2 40 2 55 2 70 V Minimum RST Low Time to Generate a System Reset 10 ns Reset Time Delay RST rising edge after VDD crosses VRST threshold 80 100 120 ms Missing Clock Detector Timeout Time from last system clock to res...

Page 173: ...ICL is factory calibrated to obtain a 24 5 MHz frequency Electrical specifications for the precision internal oscillator are given in Table 15 1 Note that the system clock may be derived from the programmed internal oscillator divided by 1 2 4 or 8 as defined by the IFCN bits in register OSCICN Table 15 1 Oscillator Electrical Characteristics 40 C to 85 C unless otherwise specified PARAMETER CONDI...

Page 174: ...Figure 15 3 OSCICN Internal Oscillator Control Register Bit 7 IOSCEN Internal Oscillator Enable Bit 0 Internal Oscillator Disabled 1 Internal Oscillator Enabled Bit 6 IFRDY Internal Oscillator Frequency Ready Flag 0 Internal Oscillator not running at programmed frequency 1 Internal Oscillator running at programmed frequency Bits 5 2 Reserved Bits 1 0 IFCN1 0 Internal Oscillator Frequency Control B...

Page 175: ...ted as the system clock in the same write to OSCICN External crystals and ceramic resonators typ ically require a start up time before they are settled and ready for use as the system clock The Crystal Valid Flag XTLVLD in register OSCXCN is set to 1 by hardware when the external oscillator is settled To avoid reading a false XTLVLD in crystal mode software should delay at least 1 ms between enabl...

Page 176: ...ue to match crystal frequency RC MODE Circuit from Figure 15 1 Option 2 XOSCMD 10x Choose XFCN value to match frequency range f 1 23 103 R C where f frequency of oscillation in MHz C capacitor value in pF R Pull up resistor value in kΩ C MODE Circuit from Figure 15 1 Option 3 XOSCMD 10x Choose K Factor KF for the oscillation frequency desired f KF C VDD where f frequency of oscillation in MHz C ca...

Page 177: ...hich could introduce noise or interference 15 5 External RC Example If an RC network is used as an external oscillator source for the MCU the circuit should be configured as shown in Figure 15 1 Option 2 The capacitor should be no greater than 100 pF however for very small capacitors the total capacitance may be dominated by parasitic capacitance in the PCB layout To determine the required Externa...

Page 178: ...n in Figure 15 8 15 7 2 PLL Multiplication and Output Clock The PLL circuitry will multiply the divided reference clock by the multiplication factor stored in the PLL0MUL reg ister shown in Figure 15 9 To accomplish this it uses a feedback loop consisting of a phase frequency detector a loop filter and a current controlled oscillator ICO It is important to configure the loop filter and the ICO for...

Page 179: ...nternal oscillator or an external clock source that is running and stable using the CLKSEL register Step 2 Ensure that the reference clock to be used for the new PLL setting internal or external is running and stable Step 3 Set the PLLSRC bit PLL0CN 2 to select the new clock source for the PLL Step 4 If moving to a faster frequency program the FLASH read timing bits FLRT FLSCL 5 4 to the appropria...

Page 180: ... static power is consumed 1 PLL bias generator is active Must be set for PLL to operate R W R W R W R R W R W R W R W Reset Value PLLLCK 0 PLLSRC PLLEN PLLPWR 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0x89 F Figure 15 8 PLL0DIV PLL Pre divider Register Bits 7 5 UNUSED Read 000b Write don t care Bits 4 0 PLLM4 0 PLL Reference Clock Pre divider These bits select the pre d...

Page 181: ...0x8E F Figure 15 10 PLL0FLT PLL Filter Register Bits 7 6 UNUSED Read 00b Write don t care Bits 5 4 PLLICO1 0 PLL Current Controlled Oscillator Control Bits Selection is based on the desired output frequency according to the following table Bits 3 0 PLLLP3 0 PLL Loop Filter Control Bits Selection is based on the divided PLL reference clock according to the following table R W R W R W R W R W R W R ...

Page 182: ... 15 3 PLL Lock Timing Characteristics 40 C to 85 C unless otherwise specified INPUT FREQUENCY MULTIPLIER PLL0MUL PLL0FLT SETTING OUTPUT FREQUENCY MIN TYP MAX UNITS 5 MHz 20 0x0F 100 MHz 202 µs 13 0x0F 65 MHz 115 µs 16 0x1F 80 MHz 241 µs 9 0x1F 45 MHz 116 µs 12 0x2F 60 MHz 258 µs 6 0x2F 30 MHz 112 µs 10 0x3F 50 MHz 263 µs 5 0x3F 25 MHz 113 µs 25 MHz 4 0x01 100 MHz 42 µs 2 0x01 50 MHz 33 µs 3 0x11 7...

Page 183: ...C8051F120 1 2 3 4 5 6 7 Rev 1 2 183 Notes ...

Page 184: ...C8051F120 1 2 3 4 5 6 7 184 Rev 1 2 ...

Page 185: ...as normal operands Before writing to FLASH memory using MOVX FLASH write operations must be enabled by setting the PSWE Program Store Write Enable bit PSCTL 0 to logic 1 This directs the MOVX writes to FLASH memory instead of to XRAM which is the default target The PSWE bit remains set until cleared by software To avoid errant FLASH writes it is recommended that interrupts be disabled while the PS...

Page 186: ...of two 128 byte pages To erase any FLASH page the FLWE PSWE and PSEE bits must be set to 1 and a byte must be written using a MOVX instruction to any address within that page The following is the recommended procedure for erasing a FLASH page from software Step 1 Disable interrupts Step 2 If erasing a page in Bank 1 Bank 2 or Bank 3 set the COBANK bits PSBANK 5 4 for the appropriate bank Step 3 If...

Page 187: ...tep 11 Re enable interrupts For block FLASH writes the FLASH write procedure is only performed after the last byte of each block is written with the MOVX write instruction When writing to addresses located in any of the four code banks a FLASH write block is four bytes long from addresses ending in 00b to addresses ending in 11b Writes must be performed sequen tially i e addresses ending in 00b 01...

Page 188: ... being read or altered across the JTAG interface Each bit in a security lock byte protects one 16k byte block of memory Access to the scratchpad area can only be locked by locking all other FLASH blocks Clearing a bit to logic 0 in a Read Lock Byte prevents the corresponding block of FLASH memory from being read across the JTAG interface Clearing a bit in the Write Erase Lock Byte protects the blo...

Page 189: ...F 0x1C000 0x1FBFD 0x14000 0x17FFF 0x10000 0x13FFF 3 2 1 0 0x08000 0x0BFFF 0x0C000 0x0FFFF 0x04000 0x07FFF 0x00000 0x03FFF Read and Write Erase Security Bits Bit 7 is MSB 0x00FF 0x0000 Scratchpad Memory Data only SFLE 1 Figure 16 2 FLASH Program Memory Map and Security Bytes FLASH Read Lock Byte Bits7 0 Each bit locks a corresponding block of memory Bit7 is MSB 0 Read operations are locked disabled...

Page 190: ... it branches to a predeter mined location in the upper partition If entry points are published software running in the upper partition may exe cute program code in the lower partition but it cannot read or change the contents of the lower partition Parameters may be passed to the program code running in the lower partition either through the typical method of placing them on the stack or in regist...

Page 191: ...z 01 SYSCLK 50 MHz 10 SYSCLK 75 MHz 11 SYSCLK 100 MHz Bits 3 1 RESERVED Read 000b Must Write 000b Bit 0 FLWE FLASH Write Erase Enable This bit must be set to allow FLASH writes erasures from user software 0 FLASH writes erases disabled 1 FLASH writes erases enabled R W R W R W R W R W R W R W R W Reset Value FLRT Reserved Reserved Reserved FLWE 10000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR ...

Page 192: ...ws an entire page of the FLASH program memory to be erased provided the PSWE bit is also set After setting this bit a write to FLASH memory using the MOVX instruction will erase the entire page that contains the location addressed by the MOVX instruction The value of the data byte written does not matter Note The FLASH page containing the Read Lock Byte and Write Erase Lock Byte cannot be erased b...

Page 193: ...r consecutive code bytes A tag contains the 15 most sig nificant bits of the corresponding FLASH address for each four byte slot Thus instruction data is always cached along four byte boundaries in code space A tag also contains a valid bit which indicates whether a cache location contains valid instruction data A special cache location called the linear tag and slot is reserved for use by the pre...

Page 194: ...ocessor is stalled during a prefetch operation for more clock cycles than the number stored in CHMSTH the requested data will be cached when it becomes available The CHMSTH bits are set to zero by default meaning that any time the processor is stalled the new data will be cached If for example CHMSTH is equal to 2 any cache miss causing a delay of 3 or 4 clock cycles will be cached while a cache m...

Page 195: ...are 0 code will execute at a fixed rate as instructions become available from the FLASH memory Cache locations can also be pre loaded and locked with time critical branch destinations For example in a system with an ISR that must respond as fast as possible the entry point for the ISR can be locked into a cache location to minimize the response latency of the ISR Up to 61 locations can be locked i...

Page 196: ... the destination of a RETI address to be cached 0 Destinations of RETI instructions will not be cached 1 RETI destinations will be cached Bit 2 CHISR Cache ISR Enable This bit allows instructions which are part of an Interrupt Service Rountine ISR to be cached 0 Instructions in ISRs will not be loaded into cache memory 1 Instructions in ISRs can be cached Bit 1 CHMOVC Cache MOVC Enable This bit al...

Page 197: ...R Page 0xA2 F Figure 17 6 CCH0LC Cache Lock Control Register Bit 7 CHPUSH Cache Push Enable This bit enables cache push operations which will lock information in cache slots using MOVC instructions 0 Cache push operations are disabled 1 Cache push operations are enabled When a MOVC read is executed the requested 4 byte segment containing the data is locked into the cache at the location indicated ...

Page 198: ...imarily used as a diagnostic feature when optimizing code for execu tion speed Writing to CHMSCTH clears the lower 5 bits of the Cache Miss Penalty Accumulator Reading from CHMSCTH returns the current value of CHMSTCH and latches bits 4 1 into CHM STCL so that they can be read Because bit 0 of the Cache Miss Penalty Accumulator is not avail able the Cumulative Miss Penalty is equal to 2 CCHMSTCH C...

Page 199: ...of these methods are given below 18 1 1 16 Bit MOVX Example The 16 bit form of the MOVX instruction accesses the memory location pointed to by the contents of the DPTR reg ister The following series of instructions reads the value of the byte at address 0x1234 into the accumulator A MOV DPTR 1234h load DPTR with 16 bit address to read 0x1234 MOVX A DPTR load contents of 0x1234 into accumulator A T...

Page 200: ...ossbar Decoder on page 217 The External Memory Interface claims the associated Port pins for memory operations ONLY during the execution of an off chip MOVX instruction Once the MOVX instruction has completed control of the Port pins reverts to the Port latches or to the Crossbar on Ports 3 2 1 and 0 See Section 19 PORT INPUT OUTPUT on page 215 for more information about the Crossbar and Port oper...

Page 201: ...accesses on chip XRAM only All effective addresses alias to on chip memory space 01 Split Mode without Bank Select Accesses below the 8k boundary are directed on chip Accesses above the 8k boundary are directed off chip 8 bit off chip MOVX operations use the current contents of the Address High port latches to resolve upper address byte Note that in order to access off chip space EMI0CN must be se...

Page 202: ...is shown in Figure 18 3 In Multiplexed mode the external MOVX operation can be broken into two phases delineated by the state of the ALE signal During the first phase ALE is high and the lower 8 bits of the Address Bus are presented to AD 7 0 During this phase the address latch is configured such that the Q outputs reflect the states of the D inputs When ALE falls signaling the beginning of the se...

Page 203: ...e not shared An example of a Non multiplexed Configuration is shown in Figure 18 4 See Section 18 6 1 Non multiplexed Mode on page 207 for more infor mation about Non multiplexed operation ADDRESS BUS E M I F A 15 0 64K X 8 SRAM A 15 0 DATA BUS D 7 0 I O 7 0 VDD 8 WR RD OE WE CE Optional Figure 18 4 Non multiplexed Configuration Example ...

Page 204: ...d off chip space Effective addresses below the 8k boundary will access on chip XRAM space Effective addresses above the 8k boundary will access off chip space 8 bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on chip or off chip However in the No Bank Select mode an 8 bit MOVX operation will not drive the upper 8 bits A 15 8 of the Address Bus during an off...

Page 205: ...emory access is on chip or off chip and the full 16 bits of the Address Bus A 15 0 are driven during the off chip transaction 18 5 4 External Only When EMI0CF 3 2 are set to 11 all MOVX operations are directed to off chip space On chip XRAM is not visi ble to the CPU This mode is useful for accessing off chip memory located between 0x0000 and the 8k boundary 8 bit MOVX operations ignore the conten...

Page 206: ...t External Memory Interface modes and MOVX operations Figure 18 6 EMI0TC External Memory Timing Control Bits7 6 EAS1 0 EMIF Address Setup Time Bits 00 Address setup time 0 SYSCLK cycles 01 Address setup time 1 SYSCLK cycle 10 Address setup time 2 SYSCLK cycles 11 Address setup time 3 SYSCLK cycles Bits5 2 EWR3 0 EMIF WR and RD Pulse Width Control Bits 0000 WR and RD pulse width 1 SYSCLK cycle 0001...

Page 207: ...RITE DATA P2 P6 P1 P5 P0 7 P4 7 P0 6 P4 6 P3 P7 T ACH T WDH T ACW T ACS T WDS ADDR 15 8 ADDR 7 0 DATA 7 0 WR RD EMIF ADDRESS 8 MSBs from DPH EMIF ADDRESS 8 LSBs from DPL P2 P6 P1 P5 P0 6 P4 6 P0 7 P4 7 P3 P7 P2 P6 P1 P5 P0 6 P4 6 P0 7 P4 7 P3 P7 T ACH T RDH T ACW T ACS T RDS ADDR 15 8 ADDR 7 0 DATA 7 0 RD WR EMIF READ DATA Nonmuxed 16 bit WRITE Nonmuxed 16 bit READ Figure 18 7 Non multiplexed 16 b...

Page 208: ...6 P4 6 P3 P7 T ACH T WDH T ACW T ACS T WDS ADDR 15 8 ADDR 7 0 DATA 7 0 WR RD EMIF ADDRESS 8 LSBs from R0 or R1 P2 P6 P1 P5 P0 6 P4 6 P0 7 P4 7 P3 P7 P2 P6 P0 6 P4 6 P0 7 P4 7 P3 P7 T ACH T RDH T ACW T ACS T RDS ADDR 15 8 ADDR 7 0 DATA 7 0 RD WR EMIF READ DATA Nonmuxed 8 bit WRITE without Bank Select Nonmuxed 8 bit READ without Bank Select Figure 18 8 Non multiplexed 8 bit MOVX without Bank Select ...

Page 209: ...6 P4 6 P3 P7 T ACH T WDH T ACW T ACS T WDS ADDR 15 8 ADDR 7 0 DATA 7 0 WR RD EMIF ADDRESS 8 MSBs from EMI0CN EMIF ADDRESS 8 LSBs from R0 or R1 P2 P6 P1 P5 P0 6 P4 6 P0 7 P4 7 P3 P7 P2 P6 P1 P5 P0 6 P4 6 P0 7 P4 7 P3 P7 T ACH T RDH T ACW T ACS T RDS ADDR 15 8 ADDR 7 0 DATA 7 0 RD WR EMIF READ DATA Nonmuxed 8 bit WRITE with Bank Select Nonmuxed 8 bit READ with Bank Select Figure 18 9 Non multiplexed...

Page 210: ... ACW T ACS T WDS ALE WR RD EMIF ADDRESS 8 MSBs from DPH EMIF WRITE DATA EMIF ADDRESS 8 LSBs from DPL T ALEH T ALEL P3 P7 P2 P6 P3 P7 ADDR 15 8 AD 7 0 P2 P6 P0 6 P4 6 P0 7 P4 7 P0 5 P4 5 P0 6 P4 6 P0 7 P4 7 P0 5 P4 5 T ACH T ACW T ACS ALE RD WR EMIF ADDRESS 8 MSBs from DPH EMIF ADDRESS 8 LSBs from DPL T ALEH T ALEL T RDH T RDS EMIF READ DATA Muxed 16 bit WRITE Muxed 16 bit READ Figure 18 10 Multipl...

Page 211: ...S T WDS ALE WR RD EMIF WRITE DATA EMIF ADDRESS 8 LSBs from R0 or R1 T ALEH T ALEL P3 P7 P2 P6 P3 P7 ADDR 15 8 AD 7 0 P0 6 P4 6 P0 7 P4 7 P0 5 P4 5 P0 6 P4 6 P0 7 P4 7 P0 5 P4 5 T ACH T ACW T ACS ALE RD WR EMIF ADDRESS 8 LSBs from R0 or R1 T ALEH T ALEL T RDH T RDS EMIF READ DATA Muxed 8 bit WRITE Without Bank Select Muxed 8 bit READ Without Bank Select Figure 18 11 Multiplexed 8 bit MOVX without B...

Page 212: ...MSBs from EMI0CN EMIF WRITE DATA EMIF ADDRESS 8 LSBs from R0 or R1 T ALEH T ALEL P3 P7 P2 P6 P3 P7 ADDR 15 8 AD 7 0 P2 P6 P0 6 P4 6 P0 7 P4 7 P0 5 P4 5 P0 6 P4 6 P0 7 P4 7 P0 5 P4 5 T ACH T ACW T ACS ALE RD WR EMIF ADDRESS 8 MSBs from EMI0CN EMIF ADDRESS 8 LSBs from R0 or R1 T ALEH T ALEL T RDH T RDS EMIF READ DATA Muxed 8 bit WRITE with Bank Select Muxed 8 bit READ with Bank Select Figure 18 12 M...

Page 213: ... 1 TSYSCLK 16 TSYSCLK ns TACH Address Control Hold Time 0 3 TSYSCLK ns TALEH Address Latch Enable High Time 1 TSYSCLK 4 TSYSCLK ns TALEL Address Latch Enable Low Time 1 TSYSCLK 4 TSYSCLK ns TWDS Write Data Setup Time 1 TSYSCLK 19 TSYSCLK ns TWDH Write Data Hold Time 0 3 TSYSCLK ns TRDS Read Data Setup Time 20 ns TRDH Read Data Hold Time 0 ns TSYSCLK is equal to one period of the device system cloc...

Page 214: ...C8051F120 1 2 3 4 5 6 7 214 Rev 1 2 Notes ...

Page 215: ...ns for the Port I O pins are given in Table 19 1 DGND PORT OUTENABLE PORT OUTPUT PUSH PULL VDD VDD WEAK PULLUP WEAK PORT PAD ANALOG INPUT Analog Select Ports 1 2 and 3 PORT INPUT Figure 19 1 Port I O Cell Block Diagram Table 19 1 Port I O DC Electrical Characteristics VDD 2 7 V to 3 6 V 40 C to 85 C unless otherwise specified PARAMETER CONDITIONS MIN TYP MAX UNITS Output High Voltage VOH IOH 3 mA ...

Page 216: ... GPIO The Port pins on Port 1 can be used as Analog Inputs to ADC2 An External Memory Interface which is active during the execution of an off chip MOVX instruction can be active on either the lower Ports or the upper Ports See Section 18 EXTERNAL DATA MEMORY INTERFACE AND ON CHIP XRAM on page 199 for more information about the External Memory Interface External Pins Digital Crossbar Priority Deco...

Page 217: ...1 respectively Because UART0 has the highest priority its pins will always be mapped to P0 0 and P0 1 when UART0EN is set to a logic 1 If a digital peripheral s enable bits are not set to a logic 1 then its ports are not accessi Figure 19 3 Priority Crossbar Decode Table PIN I O 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 TX0 RX0 SCK MISO MOSI NSS NSS is not assigned to a port ...

Page 218: ...sabled in order to prevent possible contention on the Port pins while the Crossbar registers and other registers which can affect the device pinout are being written The output drivers on Crossbar assigned input signals like RX0 for example are explicitly disabled thus the values of the Port Data registers and the PnMDOUT registers have no effect on the states of these pins 19 1 2 Configuring the ...

Page 219: ...uring the pin as an Analog Input as described below 19 1 5 Configuring Port 1 Pins as Analog Inputs The pins on Port 1 can serve as analog inputs to the ADC2 analog MUX A Port pin is configured as an Analog Input by writing a logic 0 to the associated bit in the PnMDIN registers All Port pins default to a Digital Input mode Con figuring a Port pin as an analog input 1 Disables the digital input pa...

Page 220: ...ad operations will explicitly disable the output drivers on the Data Bus See Section 18 EXTERNAL DATA MEMORY INTERFACE AND ON CHIP XRAM on page 199 for more information about the External Memory Interface Figure 19 4 Priority Crossbar Decode Table EMIFLE 1 EMIF in Multiplexed Mode P1MDIN 0xFF PIN I O 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 TX0 RX0 SCK MISO MOSI NSS NSS is n...

Page 221: ...1 2 T1 T1E XBR1 3 INT1 INT1E XBR1 4 T2 T2E XBR1 5 T2EX T2EXE XBR1 6 T4 T4E XBR2 3 T4EX T4EXE XBR2 4 SYSCLK SYSCKE XBR1 7 CNVSTR0 CNVSTE0 XBR2 0 CNVSTR2 CNVSTE2 XBR2 5 ALE RD WR AIN1 0 A8 AIN1 1 A9 AIN1 2 A10 AIN1 3 A11 AIN1 4 A12 AIN1 5 A13 AIN1 6 A14 AIN1 7 A15 A8m A0 A9m A1 A10m A2 A11m A3 A12m A4 A13m A5 A14m A6 A15m A7 AD0 D0 AD1 D1 AD2 D2 AD3 D3 AD4 D4 AD5 D5 AD6 D6 AD7 D7 XBR2 2 XBR0 5 3 UAR...

Page 222: ...t in priority order so P0 2 is assigned to SDA and P0 3 is assigned to SCL UART1 is next in priority order so P0 4 is assigned to TX1 Because the External Memory Inter face is selected on the lower Ports EMIFLE 1 which causes the Crossbar to skip P0 6 RD and P0 7 WR Because the External Memory Interface is configured in Multiplexed mode the Cross bar will also skip P0 5 ALE RX1 is assigned to the ...

Page 223: ...T1 INT1E XBR1 4 T2 T2E XBR1 5 T2EX T2EXE XBR1 6 T4 T4E XBR2 3 T4EX T4EXE XBR2 4 SYSCLK SYSCKE XBR1 7 CNVSTR0 CNVSTE0 XBR2 0 CNVSTR2 CNVSTE2 XBR2 5 ALE RD WR AIN1 0 A8 AIN1 1 A9 AIN1 2 A10 AIN1 3 A11 AIN1 4 A12 AIN1 5 A13 AIN1 6 A14 AIN1 7 A15 A8m A0 A9m A1 A10m A2 A11m A3 A12m A4 A13m A5 A14m A6 A15m A7 AD0 D0 AD1 D1 AD2 D2 AD3 D3 AD4 D4 AD5 D5 AD6 D6 AD7 D7 XBR2 2 XBR0 5 3 UART0EN SPI0EN Crossbar...

Page 224: ... CEX3 and CEX4 routed to 5 port pins 110 CEX0 CEX1 CEX2 CEX3 CEX4 and CEX5 routed to 6 port pins Bit2 UART0EN UART0 I O Enable Bit 0 UART0 I O unavailable at Port pins 1 UART0 TX routed to P0 0 and RX routed to P0 1 Bit1 SPI0EN SPI0 Bus I O Enable Bit 0 SPI0 I O unavailable at Port pins 1 SPI0 SCK MISO MOSI and NSS routed to 4 Port pins Note that the NSS signal is not assigned to a port pin if the...

Page 225: ...vailable at Port pin 1 T2 routed to Port pin Bit4 INT1E INT1 Input Enable Bit 0 INT1 unavailable at Port pin 1 INT1 routed to Port pin Bit3 T1E T1 Input Enable Bit 0 T1 unavailable at Port pin 1 T1 routed to Port pin Bit2 INT0E INT0 Input Enable Bit 0 INT0 unavailable at Port pin 1 INT0 routed to Port pin Bit1 T0E T0 Input Enable Bit 0 T0 unavailable at Port pin 1 T0 routed to Port pin Bit0 CP1E C...

Page 226: ...able at Port pins 1 UART1 TX and RX routed to 2 Port pins Bit1 EMIFLE External Memory Interface Low Port Enable Bit 0 P0 7 P0 6 and P0 5 functions are determined by the Crossbar or the Port latches 1 If EMI0CF 4 0 External Memory Interface is in Multiplexed mode P0 7 WR P0 6 RD and P0 5 ALE are skipped by the Crossbar and their output states are determined by the Port latches and the External Memo...

Page 227: ...on See also Figure 19 9 for information about configuring the Crossbar for External Memory accesses R W R W R W R W R W R W R W R W Reset Value P0 7 P0 6 P0 5 P0 4 P0 3 P0 2 P0 1 P0 0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address SFR Page 0x80 All Pages Figure 19 11 P0MDOUT Port0 Output Mode Register Bits7 0 P0MDOUT 7 0 Port0 Output Mode Bits 0 Port Pin output mode i...

Page 228: ...Memory Interface as Address 15 8 in Non multiplexed mode See Section 18 EXTERNAL DATA MEMORY INTERFACE AND ON CHIP XRAM on page 199 for more information about the External Memory Interface R W R W R W R W R W R W R W R W Reset Value P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address SFR Page 0x90 All Pages Figure 19 13 P1MDIN Port1 ...

Page 229: ...P2 7 0 Port2 Output Latch Bits Write Output appears on I O pins per XBR0 XBR1 and XBR2 Registers 0 Logic Low Output 1 Logic High Output open if corresponding P2MDOUT n bit 0 Read Regardless of XBR0 XBR1 and XBR2 Register settings 0 P2 n pin is logic low 1 P2 n pin is logic high Note P2 7 0 can be driven by the External Data Memory Interface as Address 15 8 in Multiplexed mode or as Address 7 0 in ...

Page 230: ...ts7 0 P3 7 0 Port3 Output Latch Bits Write Output appears on I O pins per XBR0 XBR1 and XBR2 Registers 0 Logic Low Output 1 Logic High Output open if corresponding P3MDOUT n bit 0 Read Regardless of XBR0 XBR1 and XBR2 Register settings 0 P3 n pin is logic low 1 P3 n pin is logic high Note P3 7 0 can be driven by the External Data Memory Interface as AD 7 0 in Multiplexed mode or as D 7 0 in Non mu...

Page 231: ...7 to Push Pull by writing PnMDOUT 0xFF 3 Force the output states of P4 P5 P6 and P7 to logic 0 by writing zeros to the Port Data registers P4 0x00 P5 0x00 P6 0x00 and P7 0x00 19 2 2 Configuring the Output Modes of the Port Pins The output mode of each port pin can be configured to be either Open Drain or Push Pull In the Push Pull configura tion a logic 0 in the associated bit in the Port Data reg...

Page 232: ... any pin that is driving a logic 0 that is an output pin will not contend with its own pull up device 19 2 5 External Memory Interface If the External Memory Interface EMIF is enabled on the High ports Ports 4 through 7 EMIFLE XBR2 5 should be set to a logic 0 If the External Memory Interface is enabled on the High ports and an off chip MOVX operation occurs the External Memory Interface will cont...

Page 233: ...ory Interface See Section 18 EXTERNAL DATA MEMORY INTERFACE AND ON CHIP XRAM on page 199 for more information R W R W R W R W R W R W R W R W Reset Value P4 7 P4 6 P4 5 P4 4 P4 3 P4 2 P4 1 P4 0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address SFR Page 0xC8 F Figure 19 20 P4MDOUT Port4 Output Mode Register Bits7 0 P4MDOUT 7 0 Port4 Output Mode Bits 0 Port Pin output mode...

Page 234: ...ode See Section 18 EXTERNAL DATA MEMORY INTERFACE AND ON CHIP XRAM on page 199 for more information about the External Memory Interface R W R W R W R W R W R W R W R W Reset Value P5 7 P5 6 P5 5 P5 4 P5 3 P5 2 P5 1 P5 0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address SFR Page 0xD8 F Figure 19 22 P5MDOUT Port5 Output Mode Register Bits7 0 P5MDOUT 7 0 Port5 Output Mode B...

Page 235: ... Non multiplexed mode See Section 18 EXTERNAL DATA MEM ORY INTERFACE AND ON CHIP XRAM on page 199 for more information about the External Memory Interface R W R W R W R W R W R W R W R W Reset Value P6 7 P6 6 P6 5 P6 4 P6 3 P6 2 P6 1 P6 0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address SFR Page 0xE8 F Figure 19 24 P6MDOUT Port6 Output Mode Register Bits7 0 P6MDOUT 7 0 ...

Page 236: ...HIP XRAM on page 199 for more information about the External Memory Interface R W R W R W R W R W R W R W R W Reset Value P7 7 P7 6 P7 5 P7 4 P7 3 P7 2 P7 1 P7 0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address SFR Page 0xF8 F Figure 19 26 P7MDOUT Port7 Output Mode Register Bits7 0 P7MDOUT 7 0 Port7 Output Mode Bits 0 Port Pin output mode is configured as Open Drain 1 P...

Page 237: ...bitration logic and START STOP control and generation Figure 20 2 shows a typical SMBus configuration The SMBus0 interface will work at any voltage between 3 0 V and 5 0 V and different devices on the bus may operate at different voltage levels The bi directional SCL serial clock Figure 20 1 SMBus0 Block Diagram SFR Bus Data Path Control SFR Bus Write to SMB0DAT SMBUS CONTROL LOGIC Read SMB0DAT SM...

Page 238: ... master devices on the same bus are supported If two or more masters attempt to initiate a data transfer simultaneously an arbitration scheme is employed with a single master always winning the arbitration Note that it is not necessary to specify one device as the master in a system any device who transmits a START and a slave address becomes the master for that transfer A typical SMBus transactio...

Page 239: ...cheme is non destructive one device always wins and no data is lost 20 2 2 Clock Low Extension SMBus provides a clock synchronization mechanism similar to I2C which allows devices with different speed capa bilities to coexist on the bus A clock low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters The slave may temporarily hold the SCL li...

Page 240: ...fter each byte To indicate the end of the serial transfer SMBus0 generates a STOP condition 20 3 2 Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL The SMBus0 interface generates a START followed by the first data byte containing the address of the target slave and the data direction bit In this case the data direction bit R W will be logic 1 to indicate ...

Page 241: ...ceives a START followed by data byte containing the slave address and direction bit If the received slave address matches the address held in register SMB0ADR the interface generates an ACK SMBus0 will also ACK if the general call address 0x00 is received and the General Call Address Enable bit SMB0ADR 0 is set to logic 1 In this case the data direc tion bit R W will be logic 0 to indicate a WRITE...

Page 242: ...r more bytes have been transferred a repeated START condition will be generated When the Stop flag STO SMB0CN 4 is set to logic 1 while the SMBus0 interface is in master mode the interface generates a STOP condition In a slave mode the STO flag may be used to recover from an error condition In this case a STOP condition is not generated on the bus but the SMBus hardware behaves as if a STOP condit...

Page 243: ...Bus Stop Flag 0 No STOP condition is transmitted 1 Setting STO to logic 1 causes a STOP condition to be transmitted When a STOP condition is received hardware clears STO to logic 0 If both STA and STO are set a STOP condition is transmit ted followed by a START condition In slave mode setting the STO flag causes SMBus to behave as if a STOP condition was received Bit3 SI SMBus Serial Interrupt Fla...

Page 244: ...hould be bounded by the following equation where SMB0CR is the unsigned 8 bit value in register SMB0CR and SYSCLK is the system clock frequency in MHz The resulting SCL signal high and low times are given by the following equations where SYSCLK is the system clock frequency in Hz Using the same value of SMB0CR from above the Bus Free Timeout period is given in the following equation R W R W R W R ...

Page 245: ...dress will be recognized Otherwise the general call address is ignored The contents of this register are ignored when SMBus0 is operating in master mode Figure 20 10 SMB0DAT SMBus0 Data Register Bits7 0 SMB0DAT SMBus0 Data The SMB0DAT register contains a byte of data to be transmitted on the SMBus0 serial interface or a byte that has just been received on the SMBus0 serial interface The CPU can re...

Page 246: ...defined when the SI flag is logic 1 Software should never write to the SMB0STA register doing so will yield indeterminate results The 28 SMBus0 states along with their corresponding status codes are given in Table 1 1 Figure 20 12 SMB0STA SMBus0 Status Register Bits7 3 STA7 STA3 SMBus0 Status Code These bits contain the SMBus0 Status Code There are 28 possible status codes each status code cor res...

Page 247: ...ge poll to retry Set STO STA 0x28 Data byte transmitted ACK received 1 Load SMB0DAT with next byte OR 2 Set STO OR 3 Clear STO then set STA for repeated START 0x30 Data byte transmitted NACK received 1 Retry transfer OR 2 Set STO 0x38 Arbitration Lost Save current data Master Receiver 0x40 Slave Address R transmitted ACK received If only receiving one byte clear AA send NACK after received byte Wa...

Page 248: ...t for next byte or STOP 0x98 Data byte received after general call address NACK transmitted Set STO to reset SMBus 0xA0 STOP or repeated START received No action necessary Slave Transmitter 0xA8 Own address R received ACK transmitted Load SMB0DAT with data to transmit 0xB0 Arbitration lost in transmitting SLA R W as master Own address R received ACK transmitted Save current data for retry when bus...

Page 249: ...n one master attempts simultaneous data transfers NSS can also be configured as a chip select output in master mode or disabled for 3 wire operation Additional general purpose port I O pins can be used to select multiple slave devices in master mode Figure 21 1 SPI Block Diagram SFR Bus Data Path Control SFR Bus Write SPI0DAT Receive Data Buffer SPI0DAT 0 1 2 3 4 5 6 7 Shift Register SPI CONTROL L...

Page 250: ...CK signal is ignored by a SPI slave when the slave is not selected NSS 1 in 4 wire slave mode 21 1 4 Slave Select NSS The function of the slave select NSS signal is dependent on the setting of the NSSMD1 and NSSMD0 bits in the SPI0CN register There are three possible modes that can be selected with these bits 1 NSSMD 1 0 00 3 Wire Master or 3 Wire Slave Mode SPI0 operates in 3 wire mode and NSS is...

Page 251: ...aster mode is active when NSSMD1 SPI0CN 3 0 and NSSMD0 SPI0CN 2 1 In this mode NSS is an input to the device and is used to disable the master SPI0 when another master is accessing the bus When NSS is pulled low in this mode MSTEN SPI0CN 6 and SPIEN SPI0CN 0 are set to 0 to disable the SPI master device and a Mode Fault is generated MODF SPI0CN 5 1 Mode Fault will generate an interrupt if enabled ...

Page 252: ...er Mode Connection Diagram Figure 21 3 3 Wire Single Master and 3 Wire Single Slave Mode Connection Diagram Slave Device Master Device MOSI MISO SCK MISO MOSI SCK Slave Device Master Device MOSI MISO SCK MISO MOSI SCK NSS NSS GPIO Slave Device MOSI MISO SCK NSS Figure 21 4 4 Wire Single Master Mode and 4 Wire Slave Mode Connection Diagram ...

Page 253: ...when NSSMD1 SPI0CN 3 0 and NSSMD0 SPI0CN 2 0 NSS is not used in this mode and is not mapped to an external port pin through the crossbar Since there is no way of uniquely addressing the device in 3 wire slave mode SPI0 must be the only slave device present on the bus It is important to note that in 3 wire slave mode there is no external means of resetting the bit counter that determines when a ful...

Page 254: ...egister is ignored when operating in slave mode When the SPI is configured as a master the maximum data transfer rate bits sec is one half the system clock frequency or 12 5 MHz whichever is slower When the SPI is con figured as a slave the maximum data transfer rate bits sec for full duplex operation is 1 10 the system clock fre quency provided that the master issues SCK NSS in 4 wire slave mode ...

Page 255: ... Bit 3 Bit 2 Bit 1 Bit 0 MOSI SCK CKPOL 0 CKPHA 0 SCK CKPOL 1 CKPHA 0 Figure 21 6 Slave Mode Data Clock Timing CKPHA 0 SCK CKPOL 0 CKPHA 1 SCK CKPOL 1 CKPHA 1 MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MISO NSS 4 Wire Mode MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MOSI Figure 21 7 Slave Mode Data Clock Timing CKPHA 1 ...

Page 256: ...us value at the NSS pin but rather a de glitched version of the pin input Bit 2 NSSIN NSS Instantaneous Pin Input read only This bit mimics the instantaneous value that is present on the NSS port pin at the time that the register is read This input is not de glitched Bit 1 SRMT Shift Register Empty Valid in Slave Mode read only This bit will be set to logic 1 when all data has been transferred in ...

Page 257: ... a previous transfer and the last bit of the current transfer is shifted into the SPI0 shift register This bit is not automatically cleared by hardware It must be cleared by software Bits 3 2 NSSMD1 NSSMD0 Slave Select Mode Selects between the following NSS operation modes See Section 21 2 SPI0 Master Mode Operation on page 251 and Section 21 3 SPI0 Slave Mode Operation on page 253 00 3 Wire Slave...

Page 258: ...is a divided version of the system clock and is given in the following equation where SYSCLK is the system clock frequency and SPI0CKR is the 8 bit value held in the SPI0CKR register for 0 SPI0CKR 255 Example If SYSCLK 2 MHz and SPI0CKR 0x04 R W R W R W R W R W R W R W R W Reset Value SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0x9D...

Page 259: ...gister is used to transmit and receive SPI0 data Writing data to SPI0DAT places the data into the transmit buffer and initiates a transfer when in Master Mode A read of SPI0DAT returns the contents of the receive buffer R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0x9B 0 ...

Page 260: ...IS MISO SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 T MIH Figure 21 12 SPI Master Timing CKPHA 0 SCK T MCKH T MCKL MISO T MIH MOSI SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 T MIS Figure 21 13 SPI Master Timing CKPHA 1 ...

Page 261: ...SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 T SEZ T SDZ Figure 21 14 SPI Slave Timing CKPHA 0 SCK T SE NSS T CKH T CKL MOSI T SIS T SIH MISO T SD T SOH SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 T SLH T SEZ T SDZ Figure 21 15 SPI Slave Timing CKPHA 1 ...

Page 262: ...e 21 14 and Figure 21 15 TSE NSS Falling to First SCK Edge 2 TSYSCLK ns TSD Last SCK Edge to NSS Rising 2 TSYSCLK ns TSEZ NSS Falling to MISO Valid 4 TSYSCLK ns TSDZ NSS Rising to MISO High Z 4 TSYSCLK ns TCKH SCK High Time 5 TSYSCLK ns TCKL SCK Low Time 5 TSYSCLK ns TSIS MOSI Valid to SCK Sample Edge 2 TSYSCLK ns TSIH SCK Sample Edge to MOSI Change 2 TSYSCLK ns TSOH SCK Shift Edge to MISO Change ...

Page 263: ...terrupt mode UART0 has two sources of interrupts a Transmit Interrupt flag TI0 SCON0 1 set when transmission of a data byte is complete and a Receive Interrupt flag RI0 SCON0 0 set when reception of a data byte is complete UART0 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine they must be cleared manually by software This allows software to determi...

Page 264: ...nsmit Interrupt Flag SCON0 1 is set at the end of the eighth bit time Data reception begins when the REN0 Receive Enable bit SCON0 4 is set to logic 1 and the RI0 Receive Interrupt Flag SCON0 0 is cleared One cycle after the eighth bit is shifted in the RI0 flag is set and recep tion stops until software clears the RI0 bit An interrupt will occur if enabled when either TI0 or RI0 are set The Mode ...

Page 265: ... and the RI0 flag will not be set An interrupt will occur if enabled when either TI0 or RI0 are set The baud rate generated in Mode 1 is a function of timer overflow shown in Equation 22 1 and Equation 22 2 UART0 can use Timer 1 operating in 8 Bit Auto Reload Mode or Timer 2 3 or 4 operating in Auto reload Mode to generate the baud rate note that the TX and RX clocks are selected separately On eac...

Page 266: ...ime Data reception can begin any time after the REN0 Receive Enable bit SCON0 4 is set to logic 1 After the stop bit is received the data byte will be loaded into the SBUF0 receive register if RI0 is logic 0 and one of the following requirements are met 1 SM20 is logic 0 2 SM20 is logic 1 the received 9th bit is logic 1 and the received address matches the UART0 address as described in Section 22 ...

Page 267: ...8 data bits LSB first a programmable ninth data bit and a stop bit The baud rate is derived from Timer 1 or Timer 2 3 or 4 overflows as defined by Equation 22 1 and Equation 22 2 Multiprocessor communica tions and hardware address recognition are supported as described in Section 22 2 Figure 22 6 UART0 Modes 1 2 and 3 Interconnect Diagram OR RS 232 C8051Fxxx RS 232 LEVEL XLTR TX RX C8051Fxxx RX TX...

Page 268: ...d include a ninth bit that is logic 1 22 2 2 Broadcast Addressing Multiple addresses can be assigned to a single slave and or a single address can be assigned to multiple slaves thereby enabling broadcast transmissions to more than one slave simultaneously The broadcast address is the logi cal OR of registers SADDR0 and SADEN0 and 0 s of the result are treated as don t cares Typically a broadcast ...

Page 269: ... Receive Overrun bit RXOVR0 in register SCON0 reads 1 if a new data byte is latched into the receive buffer before software has read the previous byte Note that the RXOVR0 bit is also used as the SM10 bit when written by user software The Frame Error bit FE0 in register SCON0 reads 1 if an invalid low STOP bit is detected Note that the FE0 bit is also used as the SM00 bit when written by user soft...

Page 270: ...1 8432 16 0xFF 0xFFFF 115200 100 0 3472 0x27 0xFF27 28800 28802 99 5328 3456 0x28 0xFF28 28800 50 0 1744 0x93 0xFF93 28800 28670 49 7664 1728 0x94 0xFF94 28800 24 0 832 0xCC 0xFFCC 28800 28846 22 1184 768 0xD0 0xFFD0 28800 18 432 640 0xD8 0xFFD8 28800 11 0592 348 0xE8 0xFFE8 28800 3 6864 128 0xF8 0xFFF8 28800 1 8432 64 0xFC 0xFFFC 28800 100 0 10416 0xFD75 9600 9601 99 5328 10368 0xFD78 9600 50 0 5...

Page 271: ... Modes 0 and 1 Set or cleared by software as required Bit2 RB80 Ninth Receive Bit The bit is assigned the logic level of the ninth bit received in Modes 2 and 3 In Mode 1 if SM20 is logic 0 RB80 is assigned the logic level of the received stop bit RB8 is not used in Mode 0 Bit1 TI0 Transmit Interrupt Flag Set by hardware when a byte of data has been transmitted by UART0 after the 8th bit in Mode 0...

Page 272: ...baud rate logic for configurations described in the UART0 section 0 UART0 baud rate divide by two enabled 1 UART0 baud rate divide by two disabled Bits3 2 UART0 Transmit Baud Rate Clock Selection Bits Bits1 0 UART0 Receive Baud Rate Clock Selection Bits Note FE0 RXOV0 and TXCOL0 are flags only and no interrupt is generated by these conditions R W R W R W R W R W R W R W R W Reset Value FE0 RXOV0 T...

Page 273: ...tents of this register are used to define the UART0 slave address Register SADEN0 is a bit mask to determine which bits of SADDR0 are checked against a received address corresponding bits set to logic 1 in SADEN0 are checked corresponding bits set to logic 0 are don t cares R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0xA9 0 Figu...

Page 274: ...C8051F120 1 2 3 4 5 6 7 274 Rev 1 2 Notes ...

Page 275: ...iting SBUF1 accesses the Transmit register With UART1 interrupts enabled an interrupt is generated each time a transmit is completed TI1 is set in SCON1 or a data byte has been received RI1 is set in SCON1 The UART1 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine They must be cleared manually by software allowing software to determine the cause of ...

Page 276: ...hould be set so that overflows will occur at two times the desired baud rate Note that Timer 1 may be clocked by one of five sources SYSCLK SYSCLK 4 SYSCLK 12 SYSCLK 48 or the external oscillator clock 8 For any given Timer 1 clock source the UART1 baud rate is determined by Equation 23 1 Where T1CLK is the frequency of the clock supplied to Timer 1 and T1H is the high byte of Timer 1 reload value...

Page 277: ...an begin any time after the REN1 Receive Enable bit SCON1 4 is set to logic 1 After the stop bit is received the data byte will be loaded into the SBUF1 receive register if the following conditions are met RI1 must be logic 0 and if MCE1 is logic 1 the stop bit must be logic 1 In the event of a receive data overrun the first received 8 bits are latched into the SBUF1 receive register and the follo...

Page 278: ...at the end of the transmission the beginning of the stop bit time Data reception can begin any time after the REN1 Receive Enable bit SCON1 4 is set to 1 After the stop bit is received the data byte will be loaded into the SBUF1 receive register if the following conditions are met 1 RI1 must be logic 0 and 2 if MCE1 is logic 1 the 9th bit must be logic 1 when MCE1 is logic 0 the state of the ninth...

Page 279: ...bit address If the addresses match the slave should clear its MCE1 bit to enable interrupts on the reception of the following data byte s Slaves that weren t addressed leave their MCE1 bits set and do not generate interrupts on the reception of the following data bytes thereby ignoring the data Once the entire message is received the addressed slave should reset its MCE1 bit to ignore all transmis...

Page 280: ...ssigned to the ninth transmission bit in 9 bit UART Mode It is not used in 8 bit UART Mode Set or cleared by software as required Bit2 RB81 Ninth Receive Bit RB81 is assigned the value of the STOP bit in Mode 0 it is assigned the value of the 9th data bit in Mode 1 Bit1 TI1 Transmit Interrupt Flag Set by hardware when a byte of data has been transmitted by UART1 after the 8th bit in 8 bit UART Mod...

Page 281: ...it shift register and a receive latch register When data is written to SBUF1 it goes to the transmit shift register and is held for serial transmission Writing a byte to SBUF1 is what initiates the transmission A read of SBUF1 returns the contents of the receive latch R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0x99 1 ...

Page 282: ...efinitions can be found in Section 24 1 Table 23 2 Timer Settings for Standard Baud Rates Using an External Oscillator Frequency 25 0 MHz Target Baud Rate bps Baud Rate Error Oscillator Divide Factor Timer Clock Source SCA1 SCA0 pre scale select T1M Timer 1 Reload Value hex SYSCLK from External Osc 230400 0 47 108 SYSCLK XX 1 0xCA 115200 0 45 218 SYSCLK XX 1 0x93 57600 0 01 434 SYSCLK XX 1 0x27 28...

Page 283: ...0 96 EXTCLK 8 11 0 0xFA 115200 0 00 192 EXTCLK 8 11 0 0xF4 57600 0 00 384 EXTCLK 8 11 0 0xE8 28800 0 00 768 EXTCLK 8 11 0 0xD0 14400 0 00 1536 EXTCLK 8 11 0 0xA0 9600 0 00 2304 EXTCLK 8 11 0 0x70 X Don t care SCA1 SCA0 and T1M bit definitions can be found in Section 24 1 Table 23 4 Timer Settings for Standard Baud Rates Using the PLL Frequency 50 0 MHz Target Baud Rate bps Baud Rate Error Oscillat...

Page 284: ...ide Factor Timer Clock Source SCA1 SCA0 pre scale select T1M Timer 1 Reload Value hex 230400 0 01 434 SYSCLK XX 1 0x27 115200 0 45 872 SYSCLK 4 01 0 0x93 57600 0 01 1736 SYSCLK 4 01 0 0x27 28800 0 22 3480 SYSCLK 12 00 0 0x6F 14400 0 47 6912 SYSCLK 48 10 0 0xB8 9600 0 45 10464 SYSCLK 48 10 0 0x93 X Don t care SCA1 SCA0 and T1M bit definitions can be found in Section 24 1 ...

Page 285: ...ytes a low byte TL0 or TL1 and a high byte TH0 or TH1 The Counter Timer Control register TCON is used to enable Timer 0 and Timer 1 as well as indicate their status Timer 0 interrupts can be enabled by setting the ET0 bit in the IE register Section 12 7 5 Interrupt Register Descriptions on page 149 Timer 1 interrupts can be enabled by setting the ET1 bit in the IE register Section 12 7 5 Both coun...

Page 286: ...form the 13 bit register for Timer 1 in the same manner as described above for TL0 and TH0 Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0 The input signal INT1 is used with Timer 1 24 1 2 Mode 1 16 bit Counter Timer Mode 1 operation is the same as Mode 0 except that the counter timer registers use all 16 bits The counter timers are enabled and confi...

Page 287: ...reload value in TH0 is not changed TL0 must be initial ized to the desired value before enabling the timer for the first count to be correct When in Mode 2 Timer 1 operates identically to Timer 0 Both counter timers are enabled and configured in Mode 2 in the same manner as Mode 0 Setting the TR0 bit TCON 4 enables the timer when either GATE0 TMOD 3 is logic 0 or when the input signal INT0 is low ...

Page 288: ...pt Timer 1 is inactive in Mode 3 When Timer 0 is operating in Mode 3 Timer 1 can be operated in Modes 0 1 or 2 but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt However the Timer 1 overflow can be used to generate baud rates for the SMBus and or UART and or initiate ADC conversions While Timer 0 is operating in Mode 3 Timer 1 run control is handled through it...

Page 289: ...ared by software but is automatically cleared when the CPU vectors to the External Interrupt 1 service routine if IT1 1 This flag is the inverse of the INT1 signal Bit2 IT1 Interrupt 1 Type Select This bit selects whether the configured INT1 interrupt will be falling edge sensitive or active low 0 INT1 is level triggered active low 1 INT1 is edge triggered falling edge Bit1 IE0 External Interrupt ...

Page 290: ...0 enabled only when TR0 1 AND INT0 logic 1 Bit2 C T0 Counter Timer Select 0 Timer Function Timer 0 incremented by clock defined by T0M bit CKCON 3 1 Counter Function Timer 0 incremented by high to low transitions on external input pin T0 Bits1 0 T0M1 T0M0 Timer 0 Mode Select These bits select the Timer 0 operation mode R W R W R W R W R W R W R W R W Reset Value GATE1 C T1 T1M1 T1M0 GATE0 C T0 T0M...

Page 291: ...unter Timer 0 uses the clock defined by the prescale bits SCA1 SCA0 1 Counter Timer 0 uses the system clock Bit2 UNUSED Read 0b Write don t care Bits1 0 SCA1 SCA0 Timer 0 1 Prescale Bits These bits control the division of the clock supplied to Timer 0 and or Timer 1 if configured to use prescaled clock inputs Note External clock divided by 8 is synchronized with the system clock R W R W R W R W R ...

Page 292: ... W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0x8B 0 Figure 24 9 TH0 Timer 0 High Byte Bits 7 0 TH0 Timer 0 High Byte The TH0 register is the high byte of the 16 bit Timer 0 R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0x8C 0 Figure 24 10 TH1 Timer 1 High Byte Bits 7 ...

Page 293: ...rals such as the Tn pin Timer 2 and 3 can be used to start an ADC Data Conversion and Timers 2 3 and 4 can schedule DAC outputs Only Timer 1 can be used to generate baud rates for UART 1 and Timers 1 2 3 or 4 may be used to generate baud rates for UART 0 Timer 2 3 and 4 can use either SYSCLK SYSCLK divided by 2 SYSCLK divided by 12 an external clock divided by 8 or high to low transitions on the T...

Page 294: ... 1 and an interrupt will occur if the interrupt is enabled The timer can be configured to count down by setting the Decrement Enable Bit TMRnCF 0 to 1 This will cause the timer to decrement with every timer clock count event and underflow when the timer transitions from 0x0000 to 0xFFFF Just as in overflows the Overflow Underflow Flag TFn will be set to 1 and an interrupt will occur if enabled Cou...

Page 295: ...en the value in the TMRnH and TMRnL registers matches the 16 bit value in the Reload Capture Registers RCAPnH and RCAPnL This is considered an underflow event and will cause the timer to load the value 0xFFFF The timer is automatically restarted when an underflow occurs Counter Timer with Auto Reload mode is selected by clearing the CP RLn bit Setting TRn to logic 1 enables and starts the timer In...

Page 296: ... 1 The timer should be configured via the timer clock source and reload underflow values such that the timer overflow underflows at 1 2 the desired output frequency The port pin assigned by the crossbar as the timer s output pin should be configured as a digital output see Section 19 PORT INPUT OUTPUT on page 215 Setting the timer s Run Bit TRn to 1 will start the toggle of the pin A Read Write of...

Page 297: ...Auto reload Mode If EXENn 1 TnEX should be configured as a digital input 0 Transitions on the TnEX pin are ignored 1 Transitions on the TnEX pin cause capture reload or control the direction of timer count up or down as follows Capture Mode 1 to 0 Transition on TnEX pin causes RCAPnH RCAPnL to capture timer value Auto Reload Mode DCEN 0 1 to 0 transition causes reload of timer and sets the EXFn Fl...

Page 298: ... Wave Output as follows CP RLn 0 C Tn 1 TnOE 1 Load RCAPnH RCAPnL See Square Wave Frequency Timer 2 and Timer 4 Only on page 296 Configure Port Pin to output squarewave See Section 19 PORT INPUT OUTPUT on page 215 0 Output of toggle mode not available at Timers s assigned port pin 1 Output of toggle mode available at Timers s assigned port pin Bit0 DCEN Decrement Enable Bit This bit enables the ti...

Page 299: ...te Bits 7 0 RCAP2 3 and 4H Timer 2 3 and 4 Capture Register High Byte The RCAP2 3 and 4H register captures the highballed of Timer 2 3 and 4 when Timer 2 3 and 4 is configured in capture mode When Timer 2 3 and 4 is configured in auto reload mode it holds the high byte of the reload value R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address RCAP2...

Page 300: ... and 4 Timer 2 3 and 4 High Byte The TH2 3 and 4 register contains the high byte of the 16 bit Timer 2 3 and 4 R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address TMR2H 0xCD TMR3H 0xCD TMR4H 0xCD SFR Page TMR2H page 0 TMR3H page 1 TMR4H page 2 ...

Page 301: ... by four system clock divided by twelve the external oscillator clock source divided by 8 Timer 0 overflow or an external clock signal on the ECI line Each capture compare module may be configured to operate independently in one of six modes Edge Triggered Capture Software Timer High Speed Out put Frequency Output 8 Bit PWM or 16 Bit PWM each is described in Section 25 2 The PCA is configured and ...

Page 302: ...ed by hardware when the CPU vectors to the interrupt service routine and must be cleared by software Note PCA0 interrupts must be glo bally enabled before CF interrupts are recognized PCA0 interrupts are globally enabled by setting the EA bit IE 7 and the EPCA0 bit in EIE1 to logic 1 Clearing the CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the CPU is in Idle m...

Page 303: ...EIE1 3 to logic 1 See Figure 25 3 for details on the PCA interrupt configuration Table 25 2 PCA0CPM Register Settings for PCA Capture Compare Modules PWM16 ECOM CAPP CAPN MAT TOG PWM ECCF Operation Mode X X 1 0 0 0 0 X Capture triggered by positive edge on CEXn X X 0 1 0 0 0 X Capture triggered by negative edge on CEXn X X 1 1 0 0 0 X Capture triggered by transition on CEXn X 1 0 0 1 0 0 X Softwar...

Page 304: ...ve or negative edge When a capture occurs the Capture Compare Flag CCFn in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled The CCFn bit is not automatically cleared by hardware when the CPU vec tors to the interrupt service routine and must be cleared by software Note The signal at CEXn must be high or low for at least 2 system clock cycles in order to ...

Page 305: ...s not automatically cleared by hardware when the CPU vectors to the interrupt service routine and must be cleared by software Setting the ECOMn and MATn bits in the PCA0CPMn register enables Software Timer mode Figure 25 5 PCA Software Timer Mode Diagram Match 16 bit Comparator PCA0H PCA0CPHn Enable PCA0L PCA Timebase PCA0CPLn 0 0 0 0 PCA Interrupt 0 1 x ENB ENB 0 1 Write to PCA0CPLn Write to PCA0...

Page 306: ...n MATn and ECOMn bits in the PCA0CPMn register enables the High Speed Output mode Figure 25 6 PCA High Speed Output Mode Diagram Match 16 bit Comparator PCA0H PCA0CPHn Enable PCA0L PCA Timebase PCA0CPLn PCA Interrupt 0 1 0 0 0 x ENB ENB 0 1 Write to PCA0CPLn Write to PCA0CPHn Reset PCA0CPMn P W M 1 6 n E C O M n E C C F n T O G n P W M n C A P P n C A P N n M A T n x CEXn Crossbar Port I O Toggle ...

Page 307: ...e compare module is compared to the PCA0 counter low byte on a match CEXn is toggled and the offset held in the high byte is added to the matched value in PCA0CPLn Frequency Output Mode is enabled by setting the ECOMn TOGn and PWMn bits in the PCA0CPMn register Equation 25 1 Square Wave Frequency Output Fsqr FPCA 2 PCA0CPHn Note A value of 0x00 in the PCA0CPHn register is equal to 256 for this equ...

Page 308: ...e in PCA0L overflows the CEXn output will be low see Figure 25 8 Also when the counter timer low byte PCA0L overflows from 0xFF to 0x00 PCA0CPLn is reloaded automatically with the value stored in the counter timer s high byte PCA0H without software intervention Setting the ECOMn and PWMn bits in the PCA0CPMn register enables 8 Bit Pulse Width Modulator mode The duty cycle for 8 Bit PWM Mode is giv...

Page 309: ... new value writes should be synchronized with PCA0 CCFn match interrupts 16 Bit PWM Mode is enabled by setting the ECOMn PWMn and PWM16n bits in the PCA0CPMn register For a varying duty cycle CCFn should also be set to logic 1 to enable match interrupts The duty cycle for 16 Bit PWM Mode is given by Equation 25 3 16 Bit PWM Duty Cycle DutyCycle 65536 PCA0CPn 65536 Figure 25 9 PCA 16 Bit PWM Mode P...

Page 310: ...must be cleared by software Bit3 CCF3 PCA0 Module 3 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF interrupt is enabled set ting this bit causes the CPU to vector to the CCF interrupt service routine This bit is not automati cally cleared by hardware and must be cleared by software Bit2 CCF2 PCA0 Module 2 Capture Compare Flag This bit is set by hardwar...

Page 311: ...it0 ECF PCA Counter Timer Overflow Interrupt Enable This bit sets the masking of the PCA0 Counter Timer Overflow CF interrupt 0 Disable the CF interrupt 1 Enable a PCA0 Counter Timer Overflow interrupt request when CF PCA0CN 7 is set R W R W R W R W R W R W R W R W Reset Value CIDL CPS2 CPS1 CPS0 ECF 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0xD9 0 CPS2 CPS1 CPS0 Timeba...

Page 312: ...sables the toggle function for PCA0 module n When enabled matches of the PCA0 counter with a module s capture compare register cause the logic level on the CEXn pin to tog gle If the PWMn bit is also set to logic 1 the module operates in Frequency Output Mode 0 Disabled 1 Enabled Bit1 PWMn Pulse Width Modulation Mode Enable This bit enables disables the PWM function for PCA0 module n When enabled ...

Page 313: ...00 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0xF9 0 Figure 25 13 PCA0L PCA0 Counter Timer Low Byte Bits 7 0 PCA0H PCA0 Counter Timer High Byte The PCA0H register holds the high byte MSB of the 16 bit PCA0 Counter Timer R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0xFA 0 Figure 25 14 PCA0H PCA0 Counter Timer Hig...

Page 314: ...CA0CPL5 0xE1 SFR Page PCA0CPL0 page 0 PCA0CPL1 page 0 PCA0CPL2 page 0 PCA0CPL3 page 0 PCA0CPL4 page 0 PCA0CPL5 page 0 Bits7 0 PCA0CPHn PCA0 Capture Module High Byte The PCA0CPHn register holds the high byte MSB of the 16 bit capture module n R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address PCA0CPH0 0xFC PCA0CPH1 0xFD PCA0CPH2 0xEA PCA0CPH3 0x...

Page 315: ...d There are three DR s associated with JTAG Boundary Scan and four associated with Flash read write oper ations on the MCU Figure 26 1 IR JTAG Instruction Register Reset Value 0x0000 Bit15 Bit0 IR Value Instruction Description 0x0000 EXTEST Selects the Boundary Data Register for control and observability of all device pins 0x0002 SAMPLE PRELOAD Selects the Boundary Data Register for observability ...

Page 316: ... MCU e g Bit6 P0 0 Bit8 P0 1 etc Update P0 n output enable to pin e g Bit6 P0 0oe Bit8 P0 1oe etc 7 9 11 13 15 17 19 21 Capture P0 n input from pin e g Bit7 P0 0 Bit9 P0 1 etc Update P0 n output to pin e g Bit7 P0 0 Bit9 P0 1 etc 22 24 26 28 30 32 34 36 Capture P1 n output enable from MCU Update P1 n output enable to pin 23 25 27 29 31 33 35 37 Capture P1 n input from pin Update P1 n output to pin...

Page 317: ...vides access to the standard JTAG Bypass data register 26 1 4 IDCODE Instruction The IDCODE instruction is accessed via the IR It provides access to the 32 bit Device ID register Bit Action Target 118 120 122 124 126 128 130 132 Capture P7 n output enable from MCU Update P7 n output enable to pin 119 121 123 125 127 129 131 133 Capture P7 n input from pin Update P7 n output to pin Table 26 1 Bound...

Page 318: ...an be written If the register to be written contains fewer than 18 bits the data in WriteData should be left justified i e its MSB should occupy bit 17 above This allows shorter registers to be written in fewer JTAG clock cycles For example an 8 bit register could be written by shifting only 10 bits After a Write is initiated the Busy bit should be polled to determine when the next operation can b...

Page 319: ... FLASHDAT write replaces the data in the FLASHDAT register but is otherwise ignored 001 A FLASHDAT write initiates a write of FLASHDAT into the memory address by the FLASHADR register FLASHADR is incremented by one when complete 010 A FLASHDAT write initiates an erasure sets all bytes to 0xFF of the Flash page containing the address in FLASHADR The data written must be 0xA5 for the erase to occur ...

Page 320: ...ted memory location was locked Bit0 BUSY Flash Busy Bit 0 Flash interface logic is not busy 1 Flash interface logic is processing a request Reads or writes while BUSY 1 will not initiate another operation Reset Value 0000000000 Bit9 Bit0 Figure 26 5 FLASHADR JTAG Flash Address Register This register holds the address for all JTAG Flash read write and erase operations This register autoincrements a...

Page 321: ...erals are functional and work correctly remain synchronized while debugging The Watchdog Timer WDT is disabled when the MCU is halted during single stepping or at a breakpoint The C8051F120DK is a development kit with all the hardware and software necessary to develop application code and perform in circuit debug with the C8051F12x family Each kit includes an Integrated Development Environment IDE...

Page 322: ...i bility for the functioning of undescribed features or parameters Silicon Laboratories reserves the right to make changes with out further notice Silicon Laboratories makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Silicon Laboratories assume any liability arising out of the application or use of any prod uct or circuit a...

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