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ATCA-F125 (6873M Artwork) Installation and Use (6806800J94N)
Functional Description
Functional Description
EIVPRn[PRIORITY] to 0xF (highest priority)
EIDRn[EP]
3.
Enable persistent memory feature by setting persistent memory bit inside the FPGA.
4.
Any reset may occur except power-up reset.
5. The FPGA generates an interrupt (IRQ_N[11]) to the P2020 QorIQ Integrated
Processor.
6. This external interrupt is steered through the PIC of P2020 QorIQ Integrated Processor
to the IRQ_OUT signal.
7. The IRQ_OUT signal from the interrupt controller is then automatically detected by the
DDR controller, which immediately causes main memory to enter self-refresh mode.
8.
1ms after the interrupt signal (IRQ_N[11]) the FPGA asserts the reset signal for at least
50ms.
9.
Read persistent memory bit in FPGA.
10. Initialize main memory but do not clear persistent memory area.
4.4
IPMI
The IPMI function on ATCA-F125 is implemented using the SMART Embedded Computing
common ATCA base IPMI design. This building block is based on the Pigeon Point
Systems IMPI implementation using the Renesas HD64F2166 microcontroller which is part
of the H8S controller family. The IPMI building block implementation provides the following
features:
Two IPMB interfaces to the back-plane
One local IPMB interface for on-board IPMI
One I2C/IPMB interface for intelligent or non-intelligent RTMs
One private I2C interface for non-intelligent I2C devices
Serial UART (SIPL) and KCS/LPC interfaces to the P2020 service processor
Analog voltage sensor inputs
Service processor boot flash fail over selection
Watch-dog timer
Hot swap control
Temperature sensors
