The status read back bits for the mu controller are as follows: MU_LCK: Register 0x2A bit 0
(value of 1 means the controller is locked) LST_LCK: Register 0x2A bit 1 (Value of 1 means the
control lost lock)
In order to read back the present MU Delay and phase value, it is necessary to set the Read bit
high and then low before the values can be read back: Read: Register 0x26 Bit 3 Mu Delay
Readback: Register 0x28 bits 0-7 and 0x27 bits 6,7 (Total of 9 bits in the read back the
maximum Mu delay value is d432 or x1B0) MUD_PH_Readback: Register 0x27 bits 0-4 – Phase
the controller locked to. In order to use the Mu controller in manual mode the following bits are
utilized:
Mu Controller Enable: Register 0x26 Bit 0 (Set to 0 to disable the controller)
MU_DEL_Manual: Register 0x28 bits 0-7 and 0x27 bits 7,8. (Total of 9 bits the maximum Mu
delay value is d432 or x1B0)
LVDS Receiver Controls
Downloads
Design Files
ML605 Reference Design Source Code
■
KC705 Reference Design Source Code
■
VC707 Reference Design Source Code
■
Download the AD9739A USB SPI Software and Drivers
[http://www.analog.com/en/digital-to-
analog-converters/da-converters/ad9739a/products/EVAL-AD9739A/eb.html]
■
Design
AD9739A-FMC-EBZ Schematic
■
AD9739A-FMC-EBZ Gerber Files
■
AD9739A-FMC-EBZ Layout
■
Rev A and Rev B of this board mistakenly do not follow Rule 5.62 on the ANSI/VITA 57.1
spec - “The FMC module shall connect TDI to TDO, if the module does not use the JTAG
interface.” This may cause some FMC platforms (like the VC707 and KC705) to loose JTAG
communication when this card is plugged in. It's normally a simple matter to short D30 and
D31 on the development system (sorry, this will be fixed shortly)
Third Party Bitstreams
Below is a list of hardware, IP Cores, or reference designs. While this content is believed to be
reliable, many have not been validated, verified or reviewed by Analog Devices. These
boards/platforms may or may not be suitable for end product integration or development, and
may not meet datasheet specifications. Since many of these platforms or IP Cores are not
Page 10 of 12
AD9739A Native FMC Card / Xilinx Reference Designs [Analog Devices Wiki]
5/22/2012
http://wiki.analog.com/resources/fpga/xilinx/fmc/ad9739a?force_rev=1
