Using the reference
design
Functional description
The reference design consists of two functional modules, a DDS/LVDS interface and a SPI
interface. It is part of an AXI based microblaze system as shown in the block diagram below. It is
designed to support linux running on microblaze. All other peripherals are available from Xilinx
as IP cores.
The DDS consists of a Xilinx DDS IP core and a DDR based data generator. The core generates 6
samples at every fDAC/3 clock cycles for each port of AD9739A. The frequency of the DDS as
well as the LUT entries are programmable via SDK.
The SPI interface allows programming the ADF4350 and/or AD9739A. The provided SDK
software shows the initial setup required for both the devices for a 2.5GHz DAC clock with a
300MHz single tone DDS.
Registers
QW Address
1
Bits Name
Description
0x00 31
version
32'h00_01_00_61
0x01
18
select
Data select DDS (0x0) or DDR (0x1).
17
interpolate DDR data interpolate 4x (0x1) or disabled (0x0).
16
enable
DDS enable (0x1) or disable (0x0).
15:0 phasecnt DDS phase count.
0x09 1
vdma-ovf
DMA
overflow
(W1C).
0 vdma-unf
DMA
underflow
(W1C).
1. For AXI-Lite byte addresses, multiply by 4.
2. Registers defaults to 0x0 unless otherwise specified.
Page 6 of 12
AD9739A Native FMC Card / Xilinx Reference Designs [Analog Devices Wiki]
5/22/2012
http://wiki.analog.com/resources/fpga/xilinx/fmc/ad9739a?force_rev=1
