Notes
In order to fully use the reference design, you will need to generate all the Xilinx IP's used by the
reference design yourself. The following two files are missing from the gzip file.
pcores/cf_ad9739a_core_v1_00_a/netlist/cf_ddsx_1.ngc
pcores/cf_ad9739a_core_v1_00_a/hdl/verilog/cf_ddsx_1.v
You must generate these two files using coregen. The reference design uses the following
parameters:
amplitude_mode=Full_Range
channels=1
noise_shaping=Taylor_Series_Corrected
output_selection=Sine
output_width=16
partspresent=SIN_COS_LUT_only
phase_increment=Fixed
phase_offset=None
phase_width=16
The above list is partial and only lists the key parameters for reference.
Hardware Reference
There are several hardware options available on the AD9739A-FMC-EBZ:
Clock Selection
Two clock paths are availabe to drive the clock input on the AD9739A-FMC-EBZ. The factory
default option connects the ADF4350
[http://www.analog.com/ADF4350]
to the AD9739A
[http://www.analog.com/AD9739A]
. The ADF4350
[http://www.analog.com/ADF4350]
is able to
synthesize a clock over the entire specified range of the AD9739A
[http://www.analog.com/AD9739A]
(1.6GHz to 2.5GHz).
Alternatively, an external clock can be provided via the SMA CLKIN (J3) jack. To enable this
clock path, jumper CLK SRC (P3) must be moved to the SMA 1 position. C102 and C99 on the
back of the board also need to be removed from their default position, and then soldered into
the vertical position from the large square pad they were previously soldered to and the narrow
pads closer to the ADCLK914
[http://www.analog.com/ADCLK914]
(U3). Observe the orientation
of the caps before removing them; they must be soldered with their narrow edge against the
PCB, and not the wide side as is common with most components.
SPI Source Selection
There are two options for driving the SPI port of the AD9739A
[http://www.analog.com/AD9739A]
and ADF4350
[http://www.analog.com/ADF4350]
. The first, which is used in the quick start guide
above, is to have all the SPI lines driven by the FPGA. In this case, jumper SPI SRC (P2) is set to
FMC. A level transltor ( ADG3308
[http://www.analog.com/ADG3308]
U1) is used to translate the
2.5V logic from the FPGA to the 3.3V logic required by the parts on the board.
Page 7 of 12
AD9739A Native FMC Card / Xilinx Reference Designs [Analog Devices Wiki]
5/22/2012
http://wiki.analog.com/resources/fpga/xilinx/fmc/ad9739a?force_rev=1
