Register Descriptions
12-36
ADSP-BF59x Blackfin Processor Hardware Reference
[1] A master transfer is in progress.
TWI FIFO Control Register (TWI_FIFO_CTL)
The
TWI_FIFO_CTL
register control bits affect only the FIFO and are not
tied in any way with master or slave mode operation.
Additional information for the
TWI_FIFO_CTL
register bits includes:
•
Receive buffer interrupt length
(
RCVINTLEN
)
This bit determines the rate at which receive buffer interrupts are
to be generated. Interrupts may be generated with each byte
received or after two bytes are received.
[0] An interrupt (
RCVSERV
) is set when
RCVSTAT
indicates one or
two bytes in the FIFO are full (01 or 11).
[1] An interrupt (
RCVSERV
) is set when the
RCVSTAT
field in the
TWI_FIFO_STAT
register indicates two bytes in the FIFO are full
(11).
•
Transmit buffer interrupt length
(
XMTINTLEN
)
This bit determines the rate at which transmit buffer interrupts are
to be generated. Interrupts may be generated with each byte trans-
mitted or after two bytes are transmitted.
Figure 12-22. TWI FIFO Control Register
15 14
13 12
11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TWI FIFO Control Register (TWI_FIFO_CTL)
XMTFLU
S
H (Transmit Buffer
Flush)
Reset = 0x0000
RCVFLU
S
H (Receive Buffer
Flush)
RCVINTLEN (Receive Buffer
Interrupt Length)
XMTINTLEN (Transmit Buffer
Interrupt Length)
Summary of Contents for ADSP-BF59x Blackfin
Page 64: ...Development Tools 1 22 ADSP BF59x Blackfin Processor Hardware Reference...
Page 74: ...Processor Specific MMRs 2 10 ADSP BF59x Blackfin Processor Hardware Reference...
Page 244: ...Programming Examples 6 40 ADSP BF59x Blackfin Processor Hardware Reference...
Page 700: ...Programming Examples 16 78 ADSP BF59x Blackfin Processor Hardware Reference...
Page 738: ...Boundary Scan Architecture B 8 ADSP BF59x Blackfin Processor Hardware Reference...
