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Analog Devices ADuCM355, Hardware Reference Manual

The Analog Devices ADuCM355 is a cutting-edge microcontroller for precision measurement and data acquisition applications. Unlock the full potential of this advanced device by downloading the comprehensive Hardware Reference Manual for free at 88.208.23.73:8080. The manual provides essential insights and technical details to help you harness the power of ADuCM355.

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UG-1262 

ADuCM355

 Hardware Reference Manual

 

Rev. B | Page 228 of 312 

Low = REQD_LOW_TIME/PCLK_PERIOD

 – 1 

where 

REQD_LOW_TIME

 is the required low time period. 

For 100 kHz SCL operation with a low time of 5 μs, a high time of 5 μs, and a PCLK frequency of 26 MHz, 

High

 = (5 μs/(1/26,000,000)) − 2 = 128 = 0x80 

   

 

 

 

 

 

 

(22) 

Low

 = (5 μs/(1/26,000,000)) − 1 = 129 = 0x81 

   

 

 

 

 

 

 

(23) 

f

SCL

 = 26,000,000/(128 + 129 + 3) = 100 kHz 

   

 

 

 

 

 

 

(24) 

Resetting the I

2

C Block 

Three steps are needed to reset the I

2

C block. Do not reset the I

2

C peripheral on two consecutive communication sequences. 

In master mode, the steps are as follows: 

1.

 

Clear MCTL, Bit 0 to 0 and disable the I

2

C master. 

2.

 

Set SHCTL, Bit 0 to 1, which is a write only register. Writing to this bit resets the start and stop detection circuits of the I

2

C block 

and clears MSTAT, Bit 10.  

3.

 

Set MCTL, Bit 0 to 1 to reenable the I

2

C master. 

In slave mode, the steps are as follows: 

1.

 

Clear SCTL, Bit 0 to 0 and disable the I

2

C slave. 

2.

 

Set SHCTL, Bit 0 to 1, which is a write only register. Writing to this bit resets the start and stop detection circuits of the I

2

C block. 

3.

 

Set SCTL, Bit 0 to 1 to reenable the I

2

C slave. 

I

2

C OPERATING MODES 

Master Transfer Initiation 

If the master enable bit (MCTL, Bit 0) is set, a master transfer sequence is initiated by writing a value to the ADR1 register. If there is 
valid data in the MTX register, it is the first byte transferred in the sequence after the address byte during a write sequence. 

Slave Transfer Initiation 

If the slave enable bit (SCTL, Bit 0) is set, a slave transfer sequence is monitored for the device address in Register ID0, Register ID1, 
Register ID2, or Register ID3. If the device address is recognized, the device participates in the slave transfer sequence. 

Note that a slave operation always starts with the assertion of one of three interrupt sources: a read request (MRXREQ, SRXREQ), a write 
request (MTXREQ, STXREQ), or a general call interrupt (GCINT). The software must always look for a stop interrupt to ensure that the 
transaction has completed correctly and to deassert the stop interrupt status bit. 

Receive and Transmit Data FIFOs 

The transmit data path consists of a master and slave transmit FIFO (each two bytes deep), the MTX register and STX register, and a 
transmit shifter. The transmit status bits, MSTAT, Bits[1:0] and SSTAT, Bit 0 denote whether there is valid data in the transmit FIFO. 
Data from the transmit FIFO is loaded into the transmit shifter when a serial byte begins transmission. If the transmit FIFO is not full 
during an active transfer sequence, the transmit request bit (MSTAT, Bit 2 or SSTAT, Bit 2) asserts. Figure 60 shows the effect of not 
having the slave transmit FIFO full at the start of a read request from a master. An extra transmit interrupt can be generated after the 
read bit. This extra transmit interrupt occurs if the transmit FIFO is not full.  

RE

A

D

DEVICE

ADDRESS

I2C_SDA

LINE

ACK

NO

 ACK

AC

K

AC

K

AC

K

ST

O

P

R/

W

DATA (n + 2)

DATA (n + x)

DATA (n + 1)

DATA (n)

TRANSMIT

INTERRUPT

TRANSMIT

INTERRUPT

EXTRA TRANSMIT INTERRUPT
POSSIBLE IF FIFO LOADED IN
PREVIOUS INTERRUPT

TRANSMIT

INTERRUPT

TRANSMIT

INTERRUPT

TRANSMIT

INTERRUPT

166

75-

043

 

Figure 60. I

2

C Slave Transmit Interrupt Details  

Summary of Contents for ADuCM355

Page 1: ...Fax 781 461 3113 www analog com ADuCM355 Hardware Reference Manual PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS Rev B Page 1 of 312 SCOPE This manual provides a detailed description of the ADuCM355 functionality and features See the ADuCM355 data sheet for the functional block diagram ...

Page 2: ...anagement Unit 29 Register Details Power Management Unit 30 Power Supply Monitor Interrupt Enable Register 30 Power Supply Monitor Status Register 30 Power Mode Register 31 Key Protection for PWRMOD and SRAMRET Register 31 Control for Retention SRAM During Hibernate Mode Register 32 HPBUCK Control Register 32 Control for SRAM Parity and Instruction SRAM Register 32 Initialization Status Register 3...

Page 3: ...n for LPTIA0 Channel Register 77 Offset Calibration LPTIA1 Channel Register 77 Gain Calibration for LPTIA1 Channel Register 77 Offset Calibration High Speed TIA Channel Register 78 Gain Calibration for High Speed TIA Channel Register 78 Offset Calibration Voltage Channel PGA Gain 1 Register 78 Gain Calibration Voltage Input Channel PGA Gain 1 Register 79 Offset Calibration Voltage Channel PGA Gain...

Page 4: ...nfiguration Register 113 Direct Write to DAC Output Control Value Register 113 DAC DC Buffer Configuration Register 113 DAC Gain Register 114 DAC Offset with Attenuator Enabled Low Power Mode Register 114 DAC Offset with Attenuator Disabled Low Power Mode Register 114 DAC Offset with Attenuator Enabled High Power Mode Register 115 DAC Offset with Attenuator Disabled High Power Mode Register 115 Wa...

Page 5: ... Register 178 Channel Request Mask Clear Register 178 Channel Enable Set Register 179 Channel Enable Clear Register 179 Channel Primary Alternate Set Register 179 Channel Primary Alternate Clear Register 180 Channel Priority Set Register 180 Channel Priority Clear Register 180 Bus Error Clear Register 181 Per Channel Bus Error Register 181 Per Channel Invalid Descriptor Clear Register 181 Channel ...

Page 6: ... Digital Inputs and Outputs Operation 215 Interrupts 215 Digital Die Port Mux 217 AFE Die Digital Port Mux 217 Register Summary Digital Inputs and Outputs 218 Register Details Digital Inputs and Outputs 220 GPIO Port Configuration Registers 220 GPIO Port Output Enable Registers 220 GPIO Port Input Output Pull Up Enable Registers 220 GPIO Port Input Path Enable Registers 221 GPIO Port Registered Da...

Page 7: ... Registers 254 Flow Control Registers 255 Wait Timer for Flow Control Registers 255 Chip Select Override Registers 255 UART Serial Interface 256 UART Overview 256 UART Features 256 UART Operation 256 Register Summary UART 259 Register Details UART 260 Transmit Holding Register 260 Receive Buffer Register 260 Interrupt Enable Register 260 Interrupt Identification Register 261 Line Control Register ...

Page 8: ...Watchdog Timer Control Register 284 Refresh Watchdog Register 285 Timer Status Register 285 Minimum Load Value Register 286 Digital Die Wake Up Timer 287 Overview 287 Features 287 Regular and Periodic Modulo 60 Interrupts 287 Timer Matching Alarm Value Interrupts 287 WUT Functional Description 287 WUT Operating Modes 288 WUT Recommendations Clock and Power 288 Register Summary Digital Die Wake Up ...

Page 9: ...emical Impedance Spectroscopy Section 91 Changes to Table 109 93 Changes to Table 111 96 Changes to Table 114 98 Changes to Table 115 99 Changes to Table 117 100 Changes to Key Features Section and Table 120 102 Changes to Using DE0 and DE1 Inputs with the High Speed TIA Section and External RTIA Selection Section 104 Changes to Table 123 106 Changes to Table 124 107 Changes to Dx Switch Matrix St...

Page 10: ... Section 161 Changes to Step 5 Calculate the Impedance of Electrochemical Sensor Sensing Electrode Node Section 162 Changes to DMA Analog Die Section and AFE Die Data FIFO Section 163 Changes to Program Flow Section 164 Change to Address Decrement Section 173 Changes to Table 219 184 Changes to Instruction vs Data SRAM Section 206 Changes to Programming Guidelines Section 208 Changes to Table 255 ...

Page 11: ...nly R W1C Memory location has read access To clear to 0 write 1 once to the memory location Memory mapped register MMR bits that are not documented are reserved When writing to MMRs with reserved bits the reserved bits must be written with the value in the reset column of the relevant MMR description unless otherwise specified Note that throughout this user guide multifunction pins such as P0 0 SP...

Page 12: ...nd slave and support for DMA Two serial peripheral interfaces SPIs with master or slave mode separate 4 byte receive and transmit FIFOs and receive and transmit DMA channels Multiple general purpose input output GPIO pins The processor of the ADuCM355 operates using the following Arm Cortex M3 processor operating from an internal 26 MHz system clock 128 kB Flash EE memory 64 kB static random acces...

Page 13: ...DIE REGISTERS 0x400C_23FF 0x400C_0800 0x4004_4FFF 0x4000_0000 0x2000_7FFF 0x2000_0000 0x1000_7FFF 0x1000_0000 0x0001_FFFF 0x0000_0000 DIGITAL DIE REGISTERS MAPPABLE SRAM MAPPABLE SRAM FLASH MEMORY UNUSED ADDRESS SPACE 16675 002 Figure 1 Arm Cortex M3 Memory Map Diagram ...

Page 14: ...equency oscillator Therefore the default values of the flash timer registers correspond to a 13 MHz clock The high power buck regulator clocks the high power buck module When the high power buck regulator is enabled this clock source is always 200 kHz The high power buck regulator is enabled and disabled by the CTL1 register in the power management unit PMU ANALOG DIE CLOCK FEATURES At power up th...

Page 15: ...1 5 16675 003 GENERAL PURPOSE TIMERS Figure 2 Clock Architecture Block Diagram CLOCK GATING In the case of certain clocks clocks can be individually gated depending on the power mode or register settings For more information about clock gating and power modes refer to the Power Management Unit section On the digital die the clock gates of the peripheral clocks are user controllable in certain powe...

Page 16: ... Selected on Digital Die Switch the digital die clock source back to a digital die clock before entering hibernate mode The device does not wake up if both die are in hibernate mode and the AFE die clock is used by both die because on waking from hibernate mode the digital die wakes first The digital die then must read or write to an AFE die register to wake the AFE die If the AFE die is the clock...

Page 17: ...0 R W Table 4 Analog Die Clock Register Summary AFECON Stack Address Name Description Reset Access 0x400C0408 CLKCON0 Clock divider configuration 0x0441 R W 0x400C0410 CLKEN1 Clock gate enable 0x010A R W 0x400C0414 CLKSEL Clock select 0x0000 R W 0x400C041C GPIOCLKMUXSEL GPIO clock mux select to GPIO1 pin 0x0000 R W 0x400C0420 CLKCON0KEY Key protection for CLKCON0 0x0000 R W 0x400C0A70 CLKEN0 Clock...

Page 18: ...scillator on Digital Die This bit indicates when the oscillator is stable after it is enabled This bit is not a monitor and does not indicate a subsequent loss of stability 0x1 R 0 Oscillator is not yet stable or is disabled 1 Oscillator is enabled stable and ready for use 7 2 Reserved Reserved 0x0 R 1 HFOSCEN High Frequency Internal Oscillator Enable This bit is used to enable and disable the hig...

Page 19: ... PCLK frequency 6 5 MHz It is recommended to only use the 0x1 0x2 or 0x4 value and matching PCLKDIVCNT with HCLKDIVCNT 0x4 R W 7 6 Reserved Reserved 0x0 R 5 0 HCLKDIVCNT HCLK Divide Count Determines the HCLK rate based on the equation HCLK root clock HCLKDIVCNT For example if the root clock is 26 MHz and HCLKDIVCNT 0x1 HCLK operates at 26 MHz The value of HCLKDIVCNT takes effect after a write acce...

Page 20: ... General Purpose Timer 2 registers 0x1 R W 0 Timer 2 clock is enabled 1 Timer 2 clock is disabled 1 GPTCLK1OFF General Purpose Timer 1 User Control This bit disables the General Purpose Timer 1 clock muxed version and controls the gate in active and flexi modes In hibernate mode the General Purpose Timer 1 clock is always off and this bit has no effect This bit is automatically cleared if user cod...

Page 21: ...on Reset Access 15 10 Reserved Reserved 0x0 R 9 AFECLKDIS AFE Die Clock Enable to AFE P2 2 Pad 0x0 R W 0 Connect AFE clock to AFE P2 2 pad 1 Disconnect AFE clock from AFE P2 2 pad 8 AFECLKSTA Reflects Status of CLKEN1 Bit Read Only 0x0 R 0 AFE clock connected to AFE die P2 2 pad 1 AFE clock disconnected from AFE die P2 2 pad 7 GPT1DIS General Purpose Timer 1 GPT1 Clock Enable This bit controls pul...

Page 22: ... clock 1 External high frequency XTAL clock 10 Internal low frequency oscillator clock Not recommended 11 External clock GPIO CLOCK MUX SELECT TO GPIO1 PIN REGISTER Address 0x400C041C Reset 0x0000 Name GPIOCLKMUXSEL Select which digital clock is output to GPIO1 for observation Table 14 Bit Descriptions for GPIOCLKMUXSEL Bits Bit Name Settings Description Reset Access 15 3 Reserved Reserved 0x0 R 2...

Page 23: ...ister A write to any other register before writing to the OSCCON register returns the protection to the lock state Table 18 Bit Descriptions for OSCCON Bits Bit Name Settings Description Reset Access 15 11 Reserved Reserved 0x0 R 10 HFXTALOK Status of HFXTAL Oscillator This bit indicates when the oscillator is stable after it is enabled This bit is not a monitor and does not indicate a subsequent ...

Page 24: ... Reserved 0x0 R 2 CLK32MHZEN 16 MHz or 32 MHz Output Selector Signal Select an output of 32 MHz or 16 MHz The ADC can run at 32 MHz but the system clock cannot run at 32 MHz Divide the system clock by 2 first before switching the oscillator to 32 MHz Refer to CLKCON0 Bits 5 0 0x1 R W 0 Select 32 MHz output 1 Select 16 MHz output 1 0 Reserved Reserved 0x0 R POWER MODE CONFIGURATION REGISTER Address...

Page 25: ...S The ADuCM355 contains two separate PMUs one for each die The PMUs control the different power modes of each ADuCM355 die The power management features of the device include the following High efficiency buck converters to reduce power on the digital die Buck converter for active mode which requires external flying capacitors as shown in the Figure 3 The buck converter is disabled by default For ...

Page 26: ...CTL5 or AFE CLKEN1 registers enables the corresponding clock to the peripheral Chip power up with the LDO regulator is on by default on both die The buck regulator can be enabled to save power consumption by writing 1 to the PMG0 CTL1 Bit 0 When enabled the input to the on chip 1 2 V LDO regulator is the buck converter output which is typically 1 6 V When the ADuCM355 wakes up from any of the low ...

Page 27: ...hibernate mode you cannot read PWRMOD after configuring it For safety reasons return value set to 0 directly return pADI_ALLON PWRMOD return 0 The following function configures the digital die operating mode int PwrCfg int iMode int iMonVbBat int iSramRet int32_t index 0 uint32_t savedWDT savedWDT pADI_WDT0 CTL None of the watchdog timer registers are retained in hibernate mode if iMode 3 Check fo...

Page 28: ...ee that the AVDD_DD supply 2 8 V to 3 6 V and the regulated supply are always within operating levels The circuit monitoring these supplies is called the PMU The main features for the PMU circuit during active mode are as follows Monitors DVDD voltage Generates a reset to the chip if AVDD_DD supply is below 1 6 V The analog die generates a reset at a higher voltage Refer to the ADuCM355 data sheet...

Page 29: ... 0x00000000 R W 0x4004C00C PWRKEY Key protection for PWRMOD and SRAMRET 0x00000000 W 0x4004C014 SRAMRET Control for retention SRAM during hibernate mode 0x00000000 R W 0x4004C044 CTL1 High power buck control 0x00000000 R W 0x4004C260 SRAM_CTL Control for SRAM parity and instruction SRAM 0x80000000 R W 0x4004C264 SRAM_INITSTAT Initialization status 0x00000001 R W Table 22 Analog Die Power Managemen...

Page 30: ...terrupt When DVDD_REG is Greater Than 1 32 V Overvoltage 0x0 R W 0 Disable VREGOVR as an interrupt source 1 Enable VREGOVR as an interrupt source 1 VREGUNDR Enable Interrupt when DVDD_REG is Less Than 1 V Undervoltage If enabled the interrupt connects to nonmaskable interrupt NMI 0x0 R W 0 Disable VREGUNDR as an interrupt source 1 Enable VREGUNDR as an interrupt source 0 VBAT Enable Interrupt for ...

Page 31: ...VDD_DD is Less than 1 8 V Generates an interrupt if IEN Bit 0 is set This bit sets if AVDD_DD 1 83 V This is a write one to clear bit The status bit sets again even after 1 is written to the flag to clear it if AVDD_DD is 1 83 V 0x0 R W1C POWER MODE REGISTER Address 0x4004C008 Reset 0x00000000 Name PWRMOD Table 25 Bit Descriptions for PWRMOD Bits Bit Name Settings Description Reset Access 31 4 Res...

Page 32: ...or is enabled CONTROL FOR SRAM PARITY AND INSTRUCTION SRAM REGISTER Address 0x4004C260 Reset 0x80000000 Name SRAM_CTL Table 29 Bit Descriptions for SRAM_CTL Bits Bit Name Settings Description Reset Access 31 INSTREN Enables Instruction SRAM 0x1 R W 1 CPU instructions use SRAM address range of 0x10000000 to 0x10003FFF 0 SRAM used for data 30 22 Reserved Reserved 0x000 R 21 PENBNK5 Enable Parity Che...

Page 33: ...Enable initialization of this bank of SRAM 3 BNK3EN Enable Initialization of SRAM Bank 3 0x0 R W 0 Disable initialization of this bank of SRAM 1 Enable initialization of this bank of SRAM 2 BNK2EN Enable Initialization of SRAM Bank 2 SRAM Address 0x10000000 to Address 0x10003FFF if SRAM_CTL Bit 31 1 Address range is 0x20004000 to 0x20007FFF if SRAM_CTL Bit 31 0 Initialization is necessary on exiti...

Page 34: ... 0 Disables the sleep and wake up timer autosleep function 1 Enables the sleep and wake up timer autosleep function 1 0 PWRMOD Power Mode Control Bits When read these bits contain the last power mode value entered by user code 0x1 R W 00 11 Reserved Do not enter this mode 01 Active Mode Normal working mode All digital circuits powered up User can optionally power down blocks by disabling their inp...

Page 35: ...o that only the actively used logic consumes dynamic power Power saving mode support hibernate mode The design has separate clocks to allow unused parts of the processor to be stopped The advanced interrupt handling features are as follows The NVIC supports up to 240 interrupts The ADuCM355 supports 64 of these interrupts The vectored interrupt feature greatly reduces interrupt latency because the...

Page 36: ...NMI input The NVIC is implemented on the ADuCM355 and more details are available in the System Exceptions and Peripheral Interrupts section Wake Up Interrupt Controller The ADuCM355 has a modified WIC that provides the lowest possible power down current See the Power Management Unit section for details It is not recommended to enter power saving mode when servicing an interrupt However if the devi...

Page 37: ...cuits and control registers The RST_STAT register indicates the source of the last reset to the digital die This register can be used during a reset exception service routine to identify the source of the reset to the digital die The RSTSTA register indicates the source of the last reset to the analog die The RSTSTA register can be used during a reset exception service routine to identify the sour...

Page 38: ... 1 and RST_STAT Bits 5 4 have information on the cause of POR reset 1 The GPIOx pins return to their default state same as a POR event 2 Random access memory RAM is not valid in the case of a reset following a UART download Software Reset Command The ARM Cortex M3 supports a software reset command Call the reset by using the following CMSIS library function NVIC_SystemReset Call Software reset Thi...

Page 39: ...Name Description Reset Access 0x4004C040 RST_STAT Digital die reset status 0x000000XX R W1C Table 35 Always On Register Summary Address Name Description Reset Access 0x400C0A40 RSTSTA Always on reset status 0x000X R W1C Table 36 Analog Die Status Register Summary Address Name Description Reset Access 0x40007008 AFEDIESTA Analog die status 0x0000 R ...

Page 40: ...riting 1 to the bit 0x0 R W1C 0 POR POR Set automatically when a POR occurs Cleared by writing 1 to the bit 0x0 R W1C ALWAYS ON RESET STATUS REGISTER Address 0x400C0A40 Reset 0x000X Name RSTSTA Table 38 Bit Descriptions for RSTSTA Bits Bit Name Settings Description Reset Access 15 3 Reserved Reserved 0xX R 2 WDRST Watchdog Timeout Set automatically to 1 when a watchdog timeout occurs Cleared by wr...

Page 41: ...ieve certain levels of system safety and reliability The level of safety is mainly dominated by system considerations and the following safety features are provided to enhance robustness Multiparity Bit Protected L1 Memories In the SRAM and cache L1 memory space each word is protected by multiple parity bits to detect the single event upsets that occur in all RAMs Debug Features The SWCLK and SWDI...

Page 42: ...r The NVIC controls the peripheral interrupts which are listed in Table 41 All interrupt sources can wake up the Arm Cortex M3 core from flexi mode Only a limited number of interrupts can wake up the processor from hibernate mode as shown in Table 41 When the device is woken up from flexi or hibernate mode it returns to active mode If the processor enters flexi or hibernate mode while the processo...

Page 43: ...ed Not applicable Not applicable 54 IRQ38 Reserved Yes No 55 IRQ39 Reserved Not applicable Not applicable 56 IRQ40 Digital Die General Purpose Timer 2 Yes No 57 IRQ41 Digital die crystal oscillator Yes No 58 IRQ42 Reserved Not applicable Not applicable 59 IRQ43 Reserved Not applicable Not applicable 60 IRQ44 Reserved Yes No 61 to 63 IRQ45 to IRQ47 Reserved Not applicable Not applicable 64 IRQ48 An...

Page 44: ...32 to IRQ63 For example to enable the General Purpose Timer 2 interrupt source in the NVIC set ISER1 Bit 8 1 Similarly to disable the General Purpose Timer 2 interrupt set ICER1 Bit 8 1 Alternatively CMSIS provides a number of useful NVIC functions in the core_cm3 h file The NVIC_EnableIRQ TMR2_EVT_IRQn function enables the General Purpose Timer 2 interrupt The interrupt can be disabled by calling...

Page 45: ...N_ADCRDYIEN Select ADCReady as interrupt source NVIC_EnableIRQ AFE_ADC_IRQn Enable AFE_ADC interrupt source in NVIC void SIP0_IRQHandler uiIntSta AfeAdcIntSta if uiIntSta BITM_AFE_ADCINTSTA_ADCRDY szADCSamples i AfeAdcRd RAWADC CLEARING ANALOG DIE INTERRUPT SOURCES IRQ48 IRQ52 IRQ54 IRQ55 and IRQ57 are interrupt sources from the analog die Ensure that the interrupt is fully serviced and the associ...

Page 46: ...pending Each bit corresponds to IRQ32 to IRQ63 in Table 41 R W 0xE000E300 IABR0 IRQ0 to IRQ31 active bits R W 0xE000E304 IABR1 IRQ32 to IRQ63 active bits R W 0xE000E400 IPR0 IRQ0 to IRQ3 priority R W 0xE000E404 IPR1 IRQ4 to IRQ7 priority R W 0xE000E408 IPR2 IRQ8 to IRQ11 priority R W 0xE000E40C IPR3 IRQ12 to IRQ15 priority R W 0xE000E410 IPR4 IRQ16 to IRQ19 priority R W 0xE000E414 IPR5 IRQ20 to IR...

Page 47: ...gh Level high or low An interrupt signal is generated and remains asserted in the NVIC until the conditions generating the interrupt deassert The level must be maintained for a minimum of one core clock cycle to be detected The external interrupt detection unit block is in the always on section and allows the external interrupt to wake up the device when in hibernate mode Ensure that the associate...

Page 48: ...x4004C080 XINT_CFG0 External interrupt Configuration 0 0x00200000 R W 0x4004C084 XINT_EXT_STAT External wake up interrupt status 0x00000000 R 0x4004C090 XINT_CLR External interrupt clear 0x00000000 R W 0x4004C094 XINT_NMICLR Nonmaskable interrupt clear 0x00000000 R W Table 45 Analog Die Global Interrupt Enable Register Summary Address Name Description Reset Access 0x400C0A28 EI2CON Analog die inte...

Page 49: ...pt on IRQ4 Refer to Table 41 0x0 R W 1 P0 11 UART_SIN wake up interrupt is enabled 0 P0 11 UART_SIN wake up interrupt is disabled 19 16 Reserved Reserved 0x0 R W 15 IRQ3EN External Interrupt 3 Enable Bit 0x0 R W 0 External Interrupt 3 disabled 1 External Interrupt 3 enabled 14 12 IRQ3MDE External Interrupt 3 Mode 0x0 R W 000 Rising edge 001 Falling edge 010 Rising or falling edge 011 High level 10...

Page 50: ...y writing 1 to XINT_CLR Bit 1 Read only register bit 0x0 R 0 External Interrupt 1 did not generate the interrupt 1 External Interrupt 1 generated the interrupt 0 Reserved Reserved 0x0 R EXTERNAL INTERRUPT CLEAR REGISTER Address 0x4004C090 Reset 0x00000000 Name XINT_CLR Table 48 Bit Descriptions for XINT_CLR Bits Bit Name Settings Description Reset Access 31 6 Reserved Reserved 0x0 R 5 UART_RX_CLR ...

Page 51: ...Descriptions for EI2CON Bits Bit Name Settings Description Reset Access 15 4 Reserved Reserved 0x0 R 3 BUSINTEN Bus Interrupt Detection Enable Bit Set before entering hibernate to enable the AFE wakeup via any analog die access 0x0 R W 0 Die interface interrupt wakeup disabled 1 Die interface interrupt wakeup enabled 2 0 Reserved Reserved Leave as 0 0x0 R W ...

Page 52: ...ns to the high speed TIA and excitation amplifier terminals See the Programmable Switches Connecting the External Sensor to the High Speed DAC and High Speed TIA section Analog die digital circuits This block includes optional programmable timers See the Analog Die General Purpose Timers section Use case configurations The Use Case Configurations section describes typical electrochemical sensor us...

Page 53: ...INTERNAL CHANNELS GAIN HSDAC D SWITCH TO CE0 CE1 RCAL0 SE1 AIN0 TO AIN3 BUF_VREF1V8 FROM RCAL0 DE0 DE1 AIN0 TO AIN3 BUF_VREF1V8 RE0 RE1 SE0 SE1 FROM RCAL1 AIN0 TO AIN3 BUF_VREF1V8 SE0 SE1 FROM RCAL1 AIN0 TO AIN3 BUF_VREF1V8 SE0 SE1 DE0 DE1 FEED BACK P SWITCHES FEED BACK N SWITCHES T SWITCHES CURRENT 1 82V PGA AAF ADC ADC MUX POSTPROCESSING DIGITAL FILTERS DFT CALIBRATION Figure 6 Block Level Overv...

Page 54: ...rdware Reference Manual Rev B Page 54 of 312 REGISTER SUMMARY ANALOG DIE CIRCUITRY Table 51 Analog Die Circuitry Register Summary Address Name Description Reset Access 0x400C2000 AFECON Analog configuration 0x00080000 R W ...

Page 55: ...ble Enable 50 Hz or 60 Hz supply rejection filter When the sinc2 digital filter is used clear this bit and set it before restarting ADC conversions 0x0 R W 0 Supply rejection filter disabled Disable sinc2 50 Hz 60 Hz digital filter Disable this bit for impedance measurements 1 Supply rejection filter enabled Enable sinc2 50 Hz 60 Hz digital filter 15 DFTEN DFT Hardware Accelerator Enable Enable th...

Page 56: ...d ADC is powered off 1 ADC enabled ADC is powered on The ADCCONVEN bit must be set to start conversions 6 HSDACEN High Speed DAC Enable Enable the high speed DAC and its reconstruction filter This bit only enables the analog block not including the DAC waveform generator 0x0 R W 0 High speed DAC disabled 1 High speed DAC enabled 5 HPREFDIS Disable High Power Reference This is the power down signal...

Page 57: ...F VZERO1 VOLTAGE INPUTS AIN0 TO AIN7 VOLTAGE INPUTS DE0 SEx CEx REx VZEROx VBIASx VOLTAGE INPUTS HIGH SPEED DACs EXCITATION AMP P AND N NODES VOLTAGE INPUTS INTERNAL CHANNELS TEMPERATURE SENSORS INTERNAL VOLTAGE REFERENCES POWER SUPPLY VOLTAGES LPTIA0 RTIA WE0 VZERO0 HSTIA RTIA 16675 108 Figure 8 ADC Input Stages ADC CIRCUIT FEATURES The ADuCM355 includes a fast multichannel 16 bit ADC The input m...

Page 58: ...lt reference source of the ADC is a precision low drift internal 1 8 V reference source Optionally connect an external reference to the VREF_1 82V and AGND_REF pins The ADC supports averaging and digital filtering options With these options the user can trade off speed and precision The highest ADC update rate is 800 kHz in low power mode or 1 6 MSPS in high power mode with no digital filtering Th...

Page 59: ...gure 10 shows the low power TIA0 input current channel low power TIA0 The low power TIA1 input current channel low power TIA1 is identical to low power TIA0 The output of the low power TIA is the voltage proportional to the input current measured by the ADC Details on how to configure the RLOAD0 resistor RTIA0 resistor and low pass filter programmable resistor RFILTER values can be found in the Lo...

Page 60: ...RRECTION DFT 8k 16k POINT DFT_CORDIC HANNING ADC MUX 800kHz 1 6MHz APB DIE TO DIE MUX 50Hz NOTCH MUX STATISTICS ADCFILTER CON 13 12 ADCFILTER CON 11 8 ADCFILTER CON 6 ADCFILTER CON 4 MUX 1 6MHz 0 8MHz ADCFILTER CON 0 MUX AVG2 4 8 16 ADCFILTER CON 7 DFTCON 0 DFTCON 21 20 DFTCON 7 4 ADCFILTER CON 15 14 STATS CON 6 4 AFECON 15 16675 011 Figure 11 ADC Postprocessing Filter Options Sinc3 Filter The inp...

Page 61: ...gital DFT The DFT accelerator is intended for use during impedance measurements To enable the DFT block set AFECON Bit 15 1 The input can be the raw ADC results sinc2 output sinc3 output ADCDAT register or the power supply filter output SINC2DAT register Configure the DFT using DFTCON Bits 21 20 The DFT outputs a complex number real and imaginary terms that represents the overall DFT result for th...

Page 62: ...DCCON Bits 12 8 01011 to select the ADC negative input channel ADCCON Bits 5 0 001011 to select the positive input channel To start an ADC conversion of the temperature sensor channel set AFECON Bit 13 and AFECON Bit 8 to 1 For optimal temperature sensor results enable chop mode of the temperature sensor with the 6 25 kHz chopping frequency Then average an even number of ADC temperature sensor res...

Page 63: ...ects the VBE_REF voltage as the ADC negative input ADCCON Bits 5 0 001011 selects the VBE voltage as the ADC positive input The 16 switches connecting different current sources to the emitter terminal of the VBE transistor are controlled by the TEMPCON1 Bits 15 0 Providing separate current sources to the VBE transistor means that a more accurate base emitter voltage can be extracted To extract the...

Page 64: ...led in Table 54 and the current selection relates to the TIA channel Example functions are provided with the EVAL ADuCM355QSPZ to demonstrate how to calibrate the ADC Table 54 Voltage Channel Offset and Gain Calibration Registers PGA Gain Setting Low Power Mode and High Power Mode Offset Registers Low Power Mode and High Power Mode Gain Registers 1 ADCOFFSETGN1 ADCGAINGN1 1 5 ADCOFFSETGN1P5 ADCGAI...

Page 65: ...itself As a new value is outputted from the digital waveform generator block to the sinc3 digital filter the digital value is shifted through the calibration block and other digital filter blocks until the digital value reaches the ADC filter result register This value can then be fed to the cyclic redundancy check CRC accelerator block on the digital die By completing the self test for a large nu...

Page 66: ...2V 0 47µF ADCVBIAS_CAP 0 47µF VREF_2 5V 1 82V REFERENCE FOR ADC BUFSENCON 0 HIGH POWER ADC BUFFER AFECON 5 1 82V REFERENCE FOR ADC AFECON 20 HIGH POWER DAC BUFFER 2 5V REFERENCE FOR LOW POWER BLOCK BUFSENCON 5 VOLTAGE REFERENCES LOW POWER 1 11V BUFFER HIGH POWER 1 11V BUFFER LOW POWER BUFFER BUFSENCON 2 LPREFBUFCON 1 LPREFBUFCON 0 LOW POWER ADC BUFFER 1 1V INTERNAL HIGH POWER PRECISION BANDGAP 1 8...

Page 67: ...tion high speed TIA channel 0x00000000 R W 0x400C2284 ADCGNHSTIA Gain calibration for high speed TIA channel 0x00004000 R W 0x400C2244 ADCOFFSETGN1 Offset calibration voltage channel PGA gain 1 0x00000000 R W 0x400C2240 ADCGAINGN1 Gain calibration voltage input channel PGA gain 1 0x00004000 R W 0x400C22CC ADCOFFSETGN1P5 Offset calibration voltage input channel PGA gain 1 5 0x00000000 R W 0x400C227...

Page 68: ...C Digital Logic Test Register Summary Optional Address Name Description Reset Access 0x400C0434 MKEY Key access for DSPUPDATEEN register 0x00000000 W 0x400C0438 DSPUPDATEEN Digital logic test enable 0x00000000 R W 0x400C2374 TEMPCON1 Temperature Sensor 1 control 0x00020000 R W ...

Page 69: ... Negative Input Signal 0x0 R W 00000 Floating input 00001 High speed TIA inverting input 00010 Low power TIA0 inverting input 00011 Low power TIA1 inverting input 00100 AIN0 00101 AIN1 00110 AIN2 00111 AIN3 BUF_VREF1V8 01000 ADCVBIAS_CAP 01001 Reserved 01010 Reserved 01011 Temperature Sensor 0 negative input 01100 AIN4_LPF0 01101 AIN5 01110 AIN6 01111 Reserved 10000 VZERO0 10001 VBIAS0 10010 VZERO...

Page 70: ...ILTERS CONFIGURATION REGISTER Address 0x400C2044 Reset 0x00000301 Name ADCFILTERCON Table 64 Bit Descriptions for ADCFILTERCON Bits Bit Name Settings Description Reset Access 31 16 Reserved Reserved 0x0 R 15 14 AVRGNUM These bits set the number of samples used by the averaging function The average output is fed directly to the DFT block and the DFT source is automatically changed to the average ou...

Page 71: ... used as DFT input 5 Reserved Reserved 0x0 R 4 LPFBYPEN 50 Hz or 60 Hz Low Pass Filter Bypass both 50 Hz and 60 Hz notch filter 0x0 R W 1 Bypass both 50 Hz notch and 60 Hz notch filters 0 Enable 50 Hz notch and 60 Hz notch filters ADC result is written to the SINC2DAT register 3 1 Reserved Reserved 0x0 R 0 ADCCLK ADC Data Rate Unfiltered ADC output rate 0x1 R W 1 800 kHz 0 1 6 MHz If ADC sample ra...

Page 72: ...t Access 31 16 Reserved Reserved 0x0 R 15 0 DATA Temperature Sensor ADC temperature sensor Channel 0 result 0x0 R W ANALOG CAPTURE INTERRUPT ENABLE REGISTER Address 0x400C2088 Reset 0x00000000 Name ADCINTIEN Table 70 Bit Descriptions for ADCINTIEN Bits Bit Name Settings Description Reset Access 31 8 Reserved Reserved 0x0 R 7 MEANIEN Mean Interrupt Mean result ready interrupt enable 0x0 R W 0 Inter...

Page 73: ...EAN register The user must write 1 to this bit to clear it Writing 0 has no effect 0x0 R W1C 0 Interrupt not asserted 1 Interrupt asserted The STATSMEAN register is ready for reading This bit generates an interrupt if ADCINTIEN Bit 7 1 6 ADCDIFFERR ADC Delta Ready ADC delta value check fail User must write 1 to this bit to clear it Writing 0 has no effect 0x0 R W1C 0 Interrupt not asserted 1 Inter...

Page 74: ...input regardless of the DFTINSEL setting 0x0 R W 00 Supply filter output Select output from low pass supply filter 01 Gain offset output with or without sinc3 Select output from ADC gain and offset correction stage If ADCFILTERCON Bit 6 is 1 filter is bypassed ADC raw data through gain or offset correction is the DFT input If the SINC3BYP bit in the ADCFILTERCON register is 0 filter is not bypasse...

Page 75: ...n mode voltage to an internal discharging circuit Ensure that the switch is open for normal operation to maintain the reference voltage on the external 1 1 V decoupling capacitor 0x0 R W 0 Open Switch Recommended value Leave the switch open to maintain the charge on external decoupling capacitor for the 1 1 V reference 1 Close Switch Close this switch to connect the 1 1 V reference to the discharg...

Page 76: ...C Conversions 0x0 R W 0 Disable repeat ADC conversions 1 Enable repeat ADC conversions BUFFER CONFIGURATION REGISTER Address 0x400C238C Reset 0x005F3D00 Name ADCBUFCON The recommended value for this register is 0x005F3D0F in high power mode and 0x005F3D04 in low power mode Table 76 Bit Descriptions for ADCBUFCON Bits Bit Name Settings Description Reset Access 31 4 Reserved Reserved 0x0 R 3 CHOPDIS...

Page 77: ...imum positive gain adjustment 0x4000 1 0 ADC result multiplied by 1 No gain adjustment Default value 0x3FFF 0 999939 minimum negative gain adjustment 0x2000 0 5 ADC result multiplied by 0 5 0x0001 0 000061 maximum negative gain adjustment 0x0000 0 Invalid value Results in an ADC result of 0 OFFSET CALIBRATION LOW POWER TIA1 CHANNEL REGISTER Address 0x400C22C0 Reset 0x00000000 Name ADCOFFSETLPTIA1 ...

Page 78: ...RATION FOR HIGH SPEED TIA CHANNEL REGISTER Address 0x400C2284 Reset 0x00004000 Name ADCGNHSTIA Table 83 Bit Descriptions for ADCGNHSTIA Bits Bit Name Settings Description Reset Access 31 15 Reserved Reserved 0x0 R 14 0 VALUE Gain Error Calibration High Speed TIA Channel 0x4000 R W 0x7FFF 2 maximum positive gain adjustment 0x4001 1 000061 minimum positive gain adjustment 0x4000 1 0 ADC result multi...

Page 79: ... Bits Bit Name Settings Description Reset Access 31 15 Reserved Reserved 0x0 R 14 0 VALUE Offset Calibration Gain 1 5 ADC offset correction with PGA gain 1 5 0x0 R W 0x3FFF 4095 75 maximum positive offset calibration value 0x0001 0 25 minimum positive offset calibration value 0x0000 0 no offset adjustment 0x7FFF 0 25 minimum negative offset calibration value 0x4000 4096 maximum negative offset cal...

Page 80: ... Reset Access 31 15 Reserved Reserved 0x0 R 14 0 VALUE Gain Calibration PGA Gain 2 ADC gain correction for voltage input channels Stored as a signed number Bit 14 is the sign bit and Bits 13 0 represent the fractional part 0x4000 R W 0x7FFF 2 maximum positive gain adjustment 0x4001 1 000061 minimum positive gain adjustment 0x4000 1 0 ADC result multiplied by 1 No gain adjustment Default value 0x3F...

Page 81: ...SETGN9 Bits Bit Name Settings Description Reset Access 31 15 Reserved Reserved 0x0 R 14 0 VALUE Offset Calibration Gain 9 ADC offset correction with PGA gain 9 0x0 R W 0x3FFF 4095 75 maximum positive offset calibration value 0x0001 0 25 minimum positive offset calibration value 0x0000 0 no offset adjustment 0x7FFF 0 25 minimum negative offset calibration value 0x4000 4096 maximum negative offset c...

Page 82: ...l ADC gain correction for temperature sensor channel Stored as a signed number Bit 14 is the sign bit and Bits 13 0 represent the fractional part 0x4000 R W 0x7FFF 2 maximum positive gain adjustment 0x4001 1 000061 minimum positive gain adjustment 0x4000 1 0 ADC result multiplied by 1 No gain adjustment Default value 0x3FFF 0 999939 minimum negative gain adjustment 0x2000 0 5 ADC result multiplied...

Page 83: ...til ADCDAT ADCMAX ADCMAXSMEN Bits 15 0 0x0 R W DELTA CHECK REGISTER Address 0x400C20B8 Reset 0x00000000 Name ADCDELTA Table 100 Bit Descriptions for ADCDELTA Bits Bit Name Settings Description Reset Access 31 16 Reserved Reserved 0x0 R 15 0 DELTAVAL ADCDAT Code Differences Limit Option If two consecutive ADCDAT results have a difference greater than ADCDELTA Bits 15 0 an error flag is set via ADCI...

Page 84: ... Name DSPUPDATEEN Table 104 Bit Descriptions for DSPUPDATEEN Bits Bit Name Settings Description Reset Access 31 1 Reserved Reserved 0x0 R W 0 DSPLOOP ADC Digital Logic Test Enable Allows high speed DAC waveform generator to create digital values that connect to the output digital logic of the ADC 0x0 R W 0 Disables digital logic test function 1 Enable digital logic test feature TEMPERATURE SENSOR ...

Page 85: ...o One Electrochemical Sensor LOW POWER TIAs Two low power TIA channels are available on the ADuCM355 The load resistor and gain resistor values are specified in the Lx registers Select the TIA gain resistor that maximizes the ADC input voltage range for the selected PGA gain setting For example if the PGA gain setting is 1 select a TIA gain resistor to maximize the 900 mV range To calculate the re...

Page 86: ...fer to the High Speed TIA Circuits section PA SW2 SW13 LPTIA SW7 10kΩ SW3 SW4 SW10 SW8 SW15 RE0 SW6 SW1 SW5 SW0 SW11 RLOAD LPTIACON0 9 5 LPTIACON0 12 10 CE0 RE0 CAP_POT0 SE0 RC0_0 RC0_1 SE0 TSWFULLCON 4 T5 TSWFULLCON 6 T7 SE1 VBIAS0 LPDACSW0 3 OPEN LPDACCON0 5 1 AND LPDACSW0 4 0 LPDACCON0 3 LPDACCON0 4 VZERO0 VREF_2 5V AIN4_LPF0 LPTIA0_P_LPF0 FORCE SENSE SW14 TO CHANNEL 1 RLPF LPTIACON0 15 13 SW9 ...

Page 87: ...CSW1 4 0 LPDACCON1 3 LPDACCON1 4 VZERO1 VREF_2 5V AIN7_LPF1 FORCE SENSE RLPF LPTIACON1 15 13 SW9 10kΩ RTIA LPDAC1 12 BIT 6 BIT LPBUF LPREF SW12 LPDACSW1 1 ADC MUX VZERO1 HSTIA ADCVBIAS_CAP 1 11V LPDACSW1 0 VZERO1 VZERO0 LPDACSW0 0 Figure 17 Low Power TIA Low Power Potentiostat and Low Power DAC Switches for Channel 1 1 6kΩ 3 1kΩ 3 6kΩ 10Ω 0Ω 10Ω 30Ω 50Ω 100Ω 20Ω 20Ω 50Ω 110Ω 890Ω 110Ω POT 1kΩ 2kΩ ...

Page 88: ...IACONx Bits 9 5 0b00000 to disconnect the internal RTIA from the TIA output terminal Close the SW9 switch by setting LPTIASWx Bit 9 1 When using the internal RTIA open the SW9 switch LOW POWER DACs The low power DACs are designed to set the sensor bias voltage In Figure 15 the sensor bias voltage is the voltage difference between the reference electrode and sense electrode Each low power DAC has t...

Page 89: ...acilitate a number of different use cases such as electrochemical impedance spectroscopy Figure 16 shows the location of the switches controlled by LPDACSWx Bits 4 0 These switches are controlled either automatically via LPDACCONx Bit 5 or individually via the LPDACSWx registers When LPDACCONx Bit 5 is cleared the switches are configured for normal mode SW2 and SW3 are closed and SW0 SW1 and SW4 a...

Page 90: ...mmended to add the following 12BITCODE LPDACDATx 11 0 6BITCODE LPDACDATx 17 12 if 12BITCODE 6BITCODE 64 LPDACDATx 11 0 12BITCODE 1 If LPDACDATx Bits 11 0 4095 the minimum voltage on the 12 bit output is 2 39946 V because LPDACDATx Bits 11 0 4095 has the same effect as LPDACDATx Bits 11 0 4094 Low Power DAC Use Cases Electrochemical Amperometric Measurement In an electrochemical measurement the 12 ...

Page 91: ... 0x0014 or 0b00 0000 0001 0100 VBIASx output generates pulse to counter electrode Capacitors on low power DACs are disconnected Low power TIA measures sense electrode current response Chronoamperometry Full Power Pulse Test Using High Speed TIA on Sense Electrode 1 0x31 0x0094 or 0b00 0000 1001 0100 VBIASx output generates pulse to counter electrode Capacitors on low power DACs are disconnected Hi...

Page 92: ...ts Channel 1 0x00000003 R W 0x400C20E0 LPTIASW1 Low power TIA switch configuration for Channel 1 0x00000000 R W Table 108 Low Power DAC Control Register Summary Address Name Description Reset Access 0x400C2120 LPDACDAT0 Low power DAC0 data out 0x00000000 R W 0x400C2124 LPDACSW0 Low power DAC0 switch control 0x00000000 R W 0x400C2128 LPDACCON0 Low power DAC0 control 0x00000002 R W 0x400C212C LPDACD...

Page 93: ...1 kΩ RTIA gain resistor must be 4 kΩ 111 3 6 kΩ RTIA gain resistor must be 4 kΩ 9 5 TIAGAIN Set RTIA 0x0 R W 0 Disconnect RTIA 1 200 Ω Intended for oxygen sensor RTIA is combination of RLOAD and a fixed series 110 Ω Assume RLOAD 10 Ω Set by the TIARL bit RTIA gain setting 100 Ω RLOAD 110 Ω fixed Overall TIA gain is 200 10 1 kΩ If RLOAD 100 Ω RTIA gain 100 Ω RLOAD 1 kΩ If RLOAD 100 Ω RTIA gain is n...

Page 94: ...fier and TIA current by half Degrades performance 1 PAPDEN Potentiostat Amplifier Power Down Low power Potentiostat Amplifier 0 power down control bit 0x1 R W 0 Power up 1 Power down 0 TIAPDEN TIA Power Down Low power TIA0 power down control bit 0x1 R W 0 Power up 1 Power down LOW POWER TIA SWITCH CONFIGURATION FOR CHANNEL 0 REGISTER Address 0x400C20E4 Reset 0x00000000 Name LPTIASW0 See Figure 16 ...

Page 95: ... switch 1 Close switch 2 SW2 SW2 Switch Control Active High 0x0 R W 0 Open switch 1 Close switch 1 SW1 SW1 Switch Control Active High 0x0 R W 0 Open switch 1 Close switch 0 SW0 SW0 Switch Control Active High 0x0 R W 0 Open switch 1 Close switch LOW POWER TIA CONTROL BITS CHANNEL 1 REGISTER Address 0x400C20E8 Reset 0x00000003 Name LPTIACON1 Table 111 Bit Descriptions for LPTIACON1 Bits Bit Name Set...

Page 96: ...1111 40 kΩ RTIA gain 40 kΩ RLOAD 100 Ω 10000 48 kΩ RTIA gain 48 kΩ RLOAD 100 Ω 10001 64 kΩ RTIA gain 64 kΩ RLOAD 100 Ω 10010 85 kΩ RTIA gain 85 kΩ RLOAD 100 Ω 10011 96 kΩ RTIA gain 96 kΩ RLOAD 100 Ω 10100 100 kΩ RTIA gain 100 kΩ RLOAD 100 Ω 10101 120 kΩ RTIA gain 120 kΩ RLOAD 100 Ω 10110 128 kΩ RTIA gain 128 kΩ RLOAD 100 Ω 10111 160 kΩ RTIA gain 160 kΩ RLOAD 100 Ω 11000 196 kΩ RTIA gain 196 kΩ RLO...

Page 97: ...ge to the VZERO0 pin 12 PABIASSEL TIA SW12 Control Active High 0x0 R W 0 Disconnect potentiostat amplifier bias voltage from the VBIAS1 pin 1 Connect potentiostat amplifier bias voltage to the VBIAS1 pin 11 SW11 SW11 Switch Control Active High 0x0 R W 0 Open switch 1 Close switch 10 SW10 SW10 Switch Control Active High 0x0 R W 0 Open switch 1 Close switch 9 SW9 SW9 Switch Control Active High 0x0 R...

Page 98: ...31 6 Reserved Reserved 0x0 R 5 LPMODEDIS Switch Control Controls switches connected to the output of low power DAC0 0x0 R W 0 Switches connected to output of low power DAC configured via LPDACCON0 Bit 5 Default 1 Overrides LPDACCON0 Bit 5 Switches connected to the low power DAC0 output are controlled via LPDACSW0 Bits 4 0 4 SW4 LPDAC0 SW4 Control 0x0 R W 0 Disconnect direct connection of VBIAS0 DA...

Page 99: ...red to 0 0x0 R W 0 VBIAS0 12 bit Default 12 bit DAC connect to VBIAS0 1 VBIAS0 6 bit 6 bit DAC connect to VBIAS0 2 REFSEL LPDAC0 Reference Select 0x0 R W 0 VREF_2 5V Reference 0 Selects the low power 2 5 V reference as the LPDAC0 reference source Default 1 AVDD Reference 1 Set to 1 to select AVDD as the low power DAC0 reference 1 PWDEN LPDAC0 Power Down Power down control bit for low power DAC 0x1...

Page 100: ...fault 0 SW0 Low Power DAC1 SW0 Control 0x0 R W 0 Disconnect VZERO1 DAC output from the high speed TIA positive input Default 1 Connect VZERO1 DAC output to the high speed TIA positive input LPDAC1 CONTROL REGISTER Address 0x400C2134 Reset 0x00000002 Name LPDACCON1 Table 118 Bit Descriptions for LPDACCON1 Bits Bit Name Settings Description Reset Access 31 7 Reserved Reserved 0x0 R 6 WAVETYPE Low Po...

Page 101: ...Reset 0x00000000 Name LPREFBUFCON Table 119 Bit Descriptions for LPREFBUFCON Bits Bit Name Settings Description Reset Access 31 3 Reserved Reserved 0x0 R 2 BOOSTCURRENT Set this Bit when Using both Channel 0 and Channel 1 Potentiostat Channels 0x0 R W 0 Option to clear to 0 when using only one potentiostat channel to support only one low power DAC and save power 1 Set to 1 to boost bias current of...

Page 102: ...ns DE0 input pin This is the Diagnostic Electrode 0 pin DE0 This pin has its own RLOAD03 and RTIA2_03 options configurable via the DE0RESCON register DE1 input pin This is the Diagnostic Electrode 1 pin DE1 This pin has its own RLOAD05 and RTIA2_05 options configurable via the DE1RESCON register The RTIA2_x options are in the 50 Ω to 160 1 kΩ range for the DE0 and DE1 inputs For all other pins the...

Page 103: ...ions are as follows Internal 1 1 V reference source same as ADCVBIAS_CAP pin voltage Sensor Channel 0 low power DAC output VZERO0 pin See Table 110 and Table 115 for details Sensor Channel 1 low power DAC output VZERO1 pin See Table 112 and Table 118 for details Figure 21 shows the high speed TIA connections to external pins and the programmable switch and resistor locations in this part of the re...

Page 104: ...the amplifier clamps the current to this limit The current clamp typically clamps at approximately 17 mA Refer to the ADuCM355 data sheet for full specifications Do not use this feature more frequently or for longer than specified in the data sheet EXTERNAL RTIA SELECTION The high speed TIA has the option of selecting an RTIA instead of the internal RTIA2 RTIA2_03 or RTIA2_05 gain options The DE0 ...

Page 105: ...more details Table 121 High Speed TIA Circuit Register Summary Address Name Description Reset Access 0x400C20F0 HSRTIACON High speed RTIA configuration 0x0000000F R W 0x400C20F4 DE1RESCON DE1 high speed TIA resistor configuration 0x000000FF R W 0x400C20F8 DE0RESCON DE0 high speed TIA resistor configuration 0x000000FF R W 0x400C20FC HSTIACON High speed TIA amplifier configuration 0x00000000 R W ...

Page 106: ...00000 0 pF 00000001 1 pF 00000010 2 pF 00000100 4 pF 00001000 8 pF 00010000 16 pF 00100000 Reserved x1xxxxxx Not used 4 TIASW6CON SW6 Control Use SW6 to select whether to use diode in parallel with RTIA or not 0x0 R W 0 SW6 off diode is not in parallel with RTIA 1 SW6 on diode is in parallel with RTIA 3 0 RTIACON Configure General RTIA Value To use this RTIA set TSWFULLCON Bit 8 1 and TSWFULLCON B...

Page 107: ...gs To use this RLOAD open the switches T9 and T11 but close T10 by setting TSWFULLCON Bits 10 8 0b010 To set the RLOAD03 and RTIA2_03 resistor values see Table 120 0xFF R W HIGH SPEED TIA AMPLIFIER CONFIGURATION REGISTER Address 0x400C20FC Reset 0x00000000 Name HSTIACON Table 125 Bit Descriptions for HSTIACON Bits Bit Name Settings Description Reset Access 31 2 Reserved Reserved 0x0 R 1 0 VBIASSEL...

Page 108: ...the sine wave amplitude The sine wave automatically swings above or below the common mode voltage As such there are only 11 bits required for the amplitude control 4 Set WGFCW Bits 23 0 to set the sine wave output frequency For output frequencies higher than 80 kHz the high speed DAC must be configured for high power mode See the Power Mode Configuration Register section for more details For this ...

Page 109: ...y is 250 kHz HIGH SPEED DAC OUTPUT ATTENUATION OPTIONS Scaling options for the high speed DAC output exist to modify the output signal amplitude to the sensor The output of the 12 bit DAC string before any attenuation or gain is approximately 300 mV At the DAC output there is a 1 or 0 2 gain stage that is controlled by HSDACCON Bit 0 At the PGA stage there is a 2 or 0 25 gain option that is contro...

Page 110: ...escribes the calibration of the high speed DAC for all gain settings in low and high power modes Calibrate the high speed DAC if it is intended to generate an excitation signal to a sensor If an offset error exists on the excitation signal and a current or voltage output must be measured the DAC output voltage can exceed the headroom of the selected TIA or ADC input buffer and PGA setting Calibrat...

Page 111: ...2 HSDACCON 0 ATTENEN 16675 129 Figure 26 High Speed DAC Calibration Circuit Using RCAL The example functions provided in the EVAL ADuCM355QSPZ kit demonstrate how to use the ADC to measure the differential voltage across RCAL and how to adjust the appropriate offset calibration resistor until this differential voltage is approximately 0 V Table 127 shows the appropriate calibration for each high s...

Page 112: ...DACOFFSET DAC offset with attenuator disabled low power mode 0x00000000 R W 0x400C22B8 DACOFFSETATTENHP DAC offset with attenuator enabled high power mode 0x00000000 R W 0x400C22BC DACOFFSETHP DAC offset with attenuator disabled high power mode 0x00000000 R W Table 129 Waveform Generator for High Speed DAC Register Summary Address Name Description Reset Access 0x400C2014 WGCON Waveform generator c...

Page 113: ...in of 1 1 DAC attenuator enabled Gain of 0 2 HSDACCON Bit 12 must also be set to 1 for this option DIRECT WRITE TO DAC OUTPUT CONTROL VALUE REGISTER Address 0x400C2048 Reset 0x00000800 Name HSDACDAT Table 131 Bit Descriptions for HSDACDAT Bits Bit Name Settings Description Reset Access 31 12 Reserved Reserved 0x0 R 11 0 DACDAT DAC Code Written directly to DAC Minimum code is 0x000 and maximum code...

Page 114: ...omplement format with a 0 5 LSB precision Used when attenuator is enabled 0x0 R W 0x7FF 210 0 5 Maximum positive adjustment Results in positive full scale 2 0 5 LSB adjustment 0x001 0 5 Results in 0 5 LSB adjustment 0x000 0 No offset adjustment 0xFFF 0 5 Results in 0 5 LSB adjustment 0x800 210 Maximum negative adjustment Results in negative full scale 2 adjustment DAC OFFSET WITH ATTENUATOR DISABL...

Page 115: ...CON Bit 0 1 Table 137 Bit Descriptions for DACOFFSETHP Bits Bit Name Settings Description Reset Access 31 12 Reserved Reserved 0x0 R 11 0 VALUE DAC Offset Correction Factor Signed number represented in twos complement format with a 0 5 LSB precision Used when attenuator is disabled 0x0 R W 0x7FF 210 0 5 Maximum positive adjustment Results in positive full scale 2 0 5 LSB adjustment 0x001 0 5 Resul...

Page 116: ...0 Reserved Reserved 0x0 R 19 0 SINEOFFSET Sinusoid Phase Offset SINOFFSET Bits 19 0 phase degrees 360 220 For example to achieve a 45 phase offset SINOFFSET Bits 19 0 45 360 220 This MMR must be set before setting WGCON Bits 2 1 and AFECON Bit 14 0x0 R W WAVEFORM GENERATOR FOR SINUSOID OFFSET REGISTER Address 0x400C2038 Reset 0x00000000 Name WGOFFSET Table 141 Bit Descriptions for WGOFFSET Bits Bi...

Page 117: ... DAC excitation amplifier output For an electrochemical gas sensor impedance measurement this pin is the CE0 or CE1 pin The Dx switches can be connected to an external calibration resistor via the RCAL0 pin if the DR0 switch is closed Px SWITCHES These switches select the pin to connect to the high speed DAC excitation amplifier P input For an electrochemical gas sensor this pin is typically RE0 o...

Page 118: ... P4 P5 P6 P7 P8 P9 P10 N P11 P12 D2 D3 D4 D5 D6 D7 D8 P2 TIA INPUT TIA OUTPUT N8 PR0 N9 RTIA2_05 RTIA2_03 T9 T10 T11 PL2 NL2 DVDD_REG_AD DSWFULLCON OR SWCON 3 0 PSWFULLCON OR SWCON 7 4 NSWFULLCON OR SWCON 11 8 TSWFULLCON OR SWCON 15 12 TSWFULLCON OR SWCON TO SET Tx SWITCHES HSRTIACON 3 0 HSRTIACON 12 5 DE0RESCON 7 0 DE1RESCON 7 0 DE1RESCON 7 0 DE0RESCON 7 0 HSRTIACON 4 DE0 DE1 HSTIACON 1 0 SELECTS...

Page 119: ...the high speed DAC Dx switches are controlled via SWCON Bits 3 0 A single external pin is selected as the D output of the excitation amplifier of the high speed DAC For SWCON Bit 16 1 each switch can be individually configured as follows The Dx switches are controlled via the DSWFULLCON register bits The Px switches are controlled via the PSWFULLCON register bits The Nx switches are controlled via...

Page 120: ...iption Reset Access 0x400C200C SWCON Switch matrix configuration 0x0000FFFF R W 0x400C2150 DSWFULLCON Dx switch matrix full configuration 0x00000000 R W 0x400C2154 NSWFULLCON Nx switch matrix full configuration 0x00000000 R W 0x400C2158 PSWFULLCON Px switch matrix full configuration 0x00000000 R W 0x400C215C TSWFULLCON Tx switch matrix full configuration 0x00000000 R W 0x400C21B0 DSWSTA Dx switch ...

Page 121: ...Switch Mux Does not Include control of T11 to T9 switches 0xF R W 0000 All switches open 0001 T1 closed others open 0010 T2 closed others open 0011 T3 closed others open 0100 T4 closed others open 0101 T5 closed others open 0110 Reserved 0111 T7 closed others open 1000 TR1 closed others open 1001 All switches closed 1010 to 1111 All switches open 11 8 NMUXCON Control of Nx Switch Mux 0xF R W 0000 ...

Page 122: ...switch settings to take effect Table 145 Bit Descriptions for DSWFULLCON Bits Bit Name Settings Description Reset Access 31 8 Reserved Reserved 0x0 R 7 D8 Control of D8 Switch Connects the D node of the excitation amplifier to the SE1 pin 0x0 R W 0 Switch open 1 Switch closed 6 D7 Control of D7 Switch Connects the D node of the excitation amplifier to the SE0 pin 0x0 R W 0 Switch open 1 Switch clo...

Page 123: ...osed 7 N8 Control of N8 Switch Set to close the N8 switch clear to open Connects the N node of the excitation amplifier to RLOAD05 T11 0x0 R W 0 Switch open 1 Switch closed 6 N7 Control of N7 Switch Set to close the N7 switch clear to open Connects the N node of the excitation amplifier to the SE1 pin via RLOAD04 0x0 R W 0 Switch open 1 Switch closed 5 N6 Control of N6 Switch Set to close the N6 s...

Page 124: ...ts the P node of the excitation amplifier to the DE1 pin 0x0 R W 0 Switch open 1 Switch closed 8 P9 Control of P9 Switch Connects the P node of the excitation amplifier to the SE1 pin 0x0 R W 0 Switch open 1 Switch closed 7 P8 Control of P8 Switch Connects the P node of the excitation amplifier to the DE0 pin 0x0 R W 0 Switch open 1 Switch closed 6 P7 Control of P7 Switch Connects the P node of th...

Page 125: ...via T10 and T11 1 Switch closed Ensure T10 and T11 are open The high speed TIA inverting input is determined by T1 T2 T3 T4 T5 and T7 7 T8 Control of T8 Switch Allows connection of the RCAL path onto the DE1 input to calibrate the RTIA2_05 resistor 0x0 R W 0 Switch open 1 Switch closed 6 T7 Control of T7 Switch Connects high speed TIA inverting input to the SE1 pin via T9 and RLOAD04 0x0 R W 0 Swi...

Page 126: ...4STA Status of D4 Switch 0x0 R 0 Switch open 1 Switch closed 2 D3STA Status of D3 Switch 0x0 R 0 Switch open 1 Switch closed 1 D2STA Status of D2 Switch 0x0 R 0 Switch open 1 Switch closed 0 D1STA Status of DR0 Switch 0x0 R 0 Switch open 1 Switch closed Px SWITCH MATRIX STATUS REGISTER Address 0x400C21B4 Reset 0x00000000 Name PSWSTA This register gives the status of the Px switches shown in Figure...

Page 127: ...Status of P4 Switch 0x0 R 0 Switch open 1 Switch closed 2 P3STA Status of P3 Switch 0x0 R 0 Switch open 1 Switch closed 1 P2STA Status of P2 Switch 0x0 R 0 Switch open 1 Switch closed 0 PR0STA PR0 Switch Control 0x0 R 0 Switch open 1 Switch closed Nx SWITCH MATRIX STATUS REGISTER Address 0x400C21B8 Reset 0x00000000 Name NSWSTA This register gives the status of the Nx switches shown in Figure 27 Ta...

Page 128: ...tus of N1 Switch 0x0 R 0 Switch open 1 Switch closed Tx SWITCH MATRIX STATUS REGISTER Address 0x400C21BC Reset 0x00000000 Name TSWSTA This register gives the status of the Tx switches shown in Figure 27 Table 152 Bit Descriptions for TSWSTA Bits Bit Name Settings Description Reset Access 31 12 Reserved Reserved 0x0 R 11 TR1STA Status of TR1 Switch 0x0 R 0 Switch open 1 Switch closed 10 T11STA Stat...

Page 129: ...T5STA Status of T5 Switch 0x0 R 0 Switch open 1 Switch closed 3 T4STA Status of T4 Switch 0x0 R 0 Switch open 1 Switch closed 2 T3STA Status of T3 Switch 0x0 R 0 Switch open 1 Switch closed 1 T2STA Status of T2 Switch 0x0 R 0 Switch open 1 Switch closed 0 T1STA Status of T1 Switch 0x0 R 0 Switch open 1 Switch closed ...

Page 130: ...mmands can be executed in succession followed by a wait command Any configuration can be rapidly set up by the sequencer regardless of the number of register writes followed by a precisely executed delay The sequencer can also be paused by setting the SEQHALT bit in the SEQCON register This option applies to each function including FIFO operations internal timers and waveform generation Reads from...

Page 131: ... the INTCCLR register The current value of the counter can be read by the host controller at any time through the SEQTIMEOUT register The timeout counter is not reset when the sequencer execution is stopped as a result of a sequencer write command However the counter resets if the host controller writes a 0 to the SEQEN bit in the SEQCON register This reset applies to situations when the host must...

Page 132: ...o set the SEQ0 to SEQ3 information sequences Each information sequence from SEQ0 to SEQ3 requires a start address in SRAM and a total number of commands for that sequence The number of commands is written to the SEQxINFO register Bits 26 16 The start address is written to the SEQxINFO register Bits 10 0 Ensure that there is no overlap between the four sequences There is no hardware mechanism in pl...

Page 133: ...format The format is shown in Figure 33 The channel ID is five bits wide with 5 b11111 indicating the DFT results Sequencer and the Sleep and Wake Up Timer See the Sleep and Wake Up Timer section for more information Sequencer Conflicts If a conflict between sequences arises for example when SEQ0 is running and the SEQ1 request arrives SEQ1 is ignored and SEQ0 completes An interrupt is generated t...

Page 134: ...x400C21E8 SEQ1INFO Sequence 1 information register 0x00000000 R W 0x400C2200 FIFOCNTSTA Command and data FIFO internal data count register 0x00000000 R 0x400C0430 TRIGSEQ Trigger sequence register 0x0000 R WS Sequencer Configuration Register Address 0x400C2004 Reset 0x00000002 Name SEQCON Table 155 Bit Descriptions for SEQCON Register Bits Bit Name Settings Description Reset Access 31 16 Reserved ...

Page 135: ...encer CRC Value Register Address 0x400C2060 Reset 0x00000001 Name SEQCRC The SEQCRC register forms the checksum value calculated from all the commands executed by the sequencer Table 157 Bit Descriptions for SEQCRC Register Bits Bit Name Description Reset Access 31 8 Reserved Reserved 0x0 R 7 0 CRC Sequencer Command CRC Value The algorithm used is CRC 8 0x1 R Sequencer Command Count Register Addre...

Page 136: ...ettings Description Reset Access 31 20 Reserved Reserved 0x0 R 19 0 SEQ_SLP_PW SEQTRGSLP Register Password These bits prevent the sequencer from accidentally triggering a sleep state 0x0 R W 0x400C Write any value other than 0xA47E5 to lock the SEQTRGSLP register 0xA47E5 Write this value to this register to unlock the SEQTRGSLP register Sequencer Trigger Sleep Register Address 0x400C211C Reset 0x0...

Page 137: ... the command is stored 0x0 R W Command Data Control Register Address 0x400C21D8 Reset 0x00000410 Name CMDDATACON Table 167 Bit Descriptions for CMDDATACON Register Bits Bit Name Settings Description Reset Access 31 12 Reserved Reserved 0x0 R 11 9 DATAMEMMDE Data FIFO Mode Select 0x2 R W 10 FIFO mode 11 Stream mode 8 6 DATA_MEM_SEL Data FIFO Size Select 0x0 R W 000 Reserved 001 2 kB SRAM 010 4 kB S...

Page 138: ... R 26 16 SEQ1INSTNUM SEQ1 Instruction Number 0x0 R W 15 11 Reserved Reserved 0x0 R 10 0 SEQ1STARTADDR SEQ1 Start Address 0x0 R W Command and Data FIFO Internal Data Count Register Address 0x400C2200 Reset 0x00000000 Name FIFOCNTSTA Table 171 Bit Descriptions for FIFOCNTSTA Register Bits Bit Name Description Reset Access 31 27 Reserved Reserved 0x0 R 26 16 DATAFIFOCNTSTA 10 0 Current Number of Word...

Page 139: ... these steps are complete the digital die is configured for INTC interrupts To configure the AFE INTC interrupts first write to the INCT0POL to configure the polarity To enable the required interrupt write to the INTCSEL0 register To clear an interrupt source write to the corresponding bit in the INTCCLR register CUSTOM INTERRUPTS Four custom interrupt sources are selectable by the user in the INT...

Page 140: ... INTCLR29 Outlier IRQ Write 1 to clear 0x0 W 28 Reserved Reserved 0x0 W 27 INTCLR27 Data FIFO Underflow IRQ Write 1 to clear 0x0 W 26 INTCLR26 Data FIFO Overflow IRQ Write 1 to clear 0x0 W 25 INTCLR25 Data FIFO Threshold IRQ Write 1 to clear 0x0 W 24 INTCLR24 Data FIFO Empty IRQ Write 1 to clear 0x0 W 23 INTCLR23 Data FIFO Full IRQ Write 1 to clear 0x0 W 22 Reserved Reserved 0x0 W 17 INTCLR17 Sequ...

Page 141: ...FIFO Threshold IRQ Enable 0x0 R W 0 Interrupt disabled 1 Interrupt enabled 24 INTSEL24 Data FIFO Empty IRQ Enable 0x0 R W 0 Interrupt disabled 1 Interrupt enabled 23 INTSEL23 Data FIFO Full IRQ Enable 0x0 R W 0 Interrupt disabled 1 Interrupt enabled 22 18 Reserved Reserved 0x0 R W 17 INTSEL17 Sequencer Timeout Error IRQ Enable 0x0 R W 0 Interrupt disabled 1 Interrupt enabled 16 INTSEL16 Sequencer ...

Page 142: ...abled 1 INTSEL1 DFT Result IRQ Enable 0x0 R W 0 Interrupt disabled 1 Interrupt enabled 0 INTSEL0 ADC Result IRQ Enable 0x0 R W 0 Interrupt disabled 1 Interrupt enabled Interrupt Controller Flag Registers Address 0x400C3010 Reset 0x00000000 Name INTCFLAG0 Address 0x400C3014 Reset 0x00000000 Name INTCFLAG1 Table 178 Bit Descriptions for INTCFLAG0 and INTCFLAG1 Registers Bits Bit Name Settings Descri...

Page 143: ...serted 1 Interrupt asserted 11 FLAG11 Custom Interrupt 2 Status 0x0 R 0 Interrupt not asserted 1 Interrupt asserted 10 FLAG10 Custom Interrupt 1 Status 0x0 R 0 Interrupt not asserted 1 Interrupt asserted 9 FLAG9 Custom Interrupt 0 Status 0x0 R 0 Interrupt not asserted 1 Interrupt asserted 8 Reserved Reserved 0x0 R 7 FLAG7 Mean IRQ Status 0x0 R 0 Interrupt not asserted 1 Interrupt asserted 6 FLAG6 ...

Page 144: ...d 1 Interrupt asserted Analog Generation Interrupt Register Address 0x400C209C Reset 0x00000010 Name AFEGENINTSTA The AFEGENINTSTA register provides custom interrupt generation Writing to this register is only possible using the sequencer Table 179 Bit Descriptions for AFEGENINTSTA Register Bits Bit Name Description Reset Access 31 4 Reserved Reserved 0x1 R 3 CUSTOMINT3 General Purpose Custom Inte...

Page 145: ...sequences can run sequentially When the timer elapses the device returns to sleep If the timer elapses before the sequence completes execution the remaining commands in the sequence are ignored Therefore the user code must ensure that the values in the SEQxSLEEPx registers are large enough to allow sequences to execute all commands It is recommended to use the wake up timer to disable the timer sl...

Page 146: ...returns to sleep mode at the end of the last sequence The maximum hibernate time is 32 seconds when using the internal 32 kHz oscillator To calculate the code for the SEQxWUPx and SEQxSLEEPx registers use the following equation Code ClkFreq Time where Code is the code value for the SEQxWUPx register ClkFreq is the frequency of the internal oscillator in Hz Time is the required timeout duration in ...

Page 147: ... timer stops at Sequence F and then goes back to Sequence A 110 The sleep and wake up timer stops at Sequence G and then goes back to Sequence A 111 The sleep and wake up timer stops at Sequence H and then goes back to Sequence A 0 EN Sleep and Wake Up Timer Enable Bit 0x0 R W 0 Disables the sleep and wake up timer 1 Enables the sleep and wake up timer Order Control Register Address 0x400C0804 Res...

Page 148: ... Reset 0xFFFF Name SEQ2WUPL Address 0x400C0838 Reset 0xFFFF Name SEQ3WUPL These registers set the sequence sleep time The counter is 20 bits These registers set the 16 LSBs When this timer elapses the device wakes up Table 183 Bit Descriptions for SEQxWUPL Registers Bits Bit Name Description Reset Access 15 0 WAKEUPTIME0 15 0 Sequence and Sleep Period This register defines the length of time in wh...

Page 149: ...me SEQ0SLEEPH Address 0x400C0824 Reset 0x000F Name SEQ1SLEEPH Address 0x400C0834 Reset 0x000F Name SEQ2SLEEPH Address 0x400C0844 Reset 0x000F Name SEQ3SLEEPH The SEQxSLEEPH registers define the device active time for SEQ0 to SEQ3 The counter is 20 bits These registers set the four MSBs Table 186 Bit Descriptions for SEQxSLEEPH Registers Bits Bit Name Description Reset Access 15 4 Reserved Reserved...

Page 150: ...xternal sensor The switches connecting the low power amplifiers to the external sensor are also unaffected when entering or exiting this mode For code examples on how to enter and exit hibernate mode see the Hibernate Mode Mode 2 section To maintain a bias voltage to an electrochemical sensor the recommended analog die configuration setting for the low power potentiostat amplifier and low power TI...

Page 151: ...N5 N4 N3 N2 N1 P P3 P4 P5 P6 P7 P8 P9 P10 N P11 P12 D2 D3 D4 D5 D6 D7 D8 P2 TIA INPUT TIA OUTPUT N8 PR0 N9 RTIA2_05 RTIA2_03 T9 T10 T11 PL2 NL2 DVDD_REG_AD DSWFULLCON OR SWCON 3 0 PSWFULLCON OR SWCON 7 4 NSWFULLCON OR SWCON 11 8 TSWFULLCON OR SWCON 15 12 TSWFULLCON OR SWCON TO SET Tx SWITCHES HSRTIACON 3 0 HSRTIACON 12 5 DE0RESCON 7 0 DE1RESCON 7 0 DE1RESCON 7 0 DE0RESCON 7 0 HSRTIACON 4 DE0 DE1 H...

Page 152: ...w pass filter ADCCON Bits 5 0 0x21 and the other is the bypassed low pass filter option ADCCON Bits 5 0 0x02 Select the low pass filter as the positive input channel of the ADC for lowest noise Select the LPTIA0 inverting input ADCCON Bits 12 8 0x2 as the ADC negative input channel Using the provided software libraries the following function call selects LPTIA0 as the ADC input AfeAdcChan MUXSELP_...

Page 153: ...ing properly Typically the current increases sharply and quickly with the step in the sensor bias voltage If the current step response is slow there can be an issue with the sensor electrolyte Implementing Pulse Test Using Low Power TIA The potentiostat and the ADC are assumed to be initially configured using the steps in the Measuring a DC Current Output section Current measurement before during ...

Page 154: ...e potentiostat for the pulse test set LPTIASWx Bits 11 0 0x094 to use the high speed TIA See the Exiting Cyclic Voltammetry Mode section for recommendations to decrease the settling time of the sensor when exiting pulse testing CYCLIC VOLTAMMETRY Cyclic voltammetry is similar to the pulse test except that both the VBIAS and VZERO outputs of the low power DAC can change to set the sensor bias volta...

Page 155: ... SW7 BIT TO SHORT LOW POWER TIA INVERTING INPUT TO THE LOW POWER TIA OUTPUT 16675 028 PA SW2 SW13 LPTIA SW7 10kΩ SW3 SW4 SW10 SW8 SW15 RE0 SW6 SW1 SW5 SW0 SW11 RLOAD LPTIACON0 9 5 LPTIACON0 12 10 CE0 RE0 SE0 RC0_0 RC0_1 SE0 TSWFULLCON 4 T5 TSWFULLCON 6 T7 SE1 VBIAS0 LPDACSW0 3 OPEN LPDACCON0 5 1 AND LPDACSW0 4 0 LPDACCON0 3 LPDACCON0 4 VZERO0 VREF_2 5V AIN4_LPF0 FORCE SENSE SW14 TO CHANNEL 1 RLPF ...

Page 156: ... NL T7 T5 T3 T4 T2 T1 N7 N6 N5 N4 N3 N2 N1 P P3 P4 P5 P6 P7 P8 P9 P10 N P11 P12 D2 D3 D4 D5 D6 D7 D8 P2 TIA INPUT TIA OUTPUT N8 PR0 N9 RTIA2_05 RTIA2_03 T9 T10 T11 PL2 NL2 DVDD_REG_AD DSWFULLCON OR SWCON 3 0 PSWFULLCON OR SWCON 7 4 NSWFULLCON OR SWCON 11 8 TSWFULLCON OR SWCON 15 12 TSWFULLCON OR SWCON TO SET Tx SWITCHES HSRTIACON 3 0 HSRTIACON 12 5 DE0RESCON 7 0 DE1RESCON 7 0 DE1RESCON 7 0 DE0RESC...

Page 157: ...uator on is approximately 607 mV 40 15 1 mV p p The voltage to the ADC is calculated as 15 1 mV RLOAD RTIA RLOAD02 is fixed at 100 Ω which gives a current of approximately 150 μA across RTIA The testing featured in this reference manual is designed for an ADC voltage of 750 mV As such set RTIA 5 kΩ The impedance measurement is performed in five steps detailed in the following sections The followin...

Page 158: ...o the ADC Step 2 Measure RLOAD02 and External Sensor RSENSOR The electrochemical sensor remains biased during this step but the working electrode voltage is set by the high speed TIA instead of the low power TIA The RLOAD02 is a fixed value load resistor 100 Ω In Figure 41 reference electrode is the sensor impedance The waveform generator and the high speed DAC generate a 10 mV amplitude sine wave...

Page 159: ... electrode and reference electrode of the electrochemical sensor are floating during this stage of the measurement sequence The main differences between Step 2 and Step 3 are as follows The reference electrode is disconnected from the excitation amplifier P node The counter electrode is disconnected from the excitation amplifier D node and is connected directly to RLOAD02 The excitation amplifier ...

Page 160: ...P N N Tx SWITCHES CLOSE T5 T9 OPEN OTHER Tx SWITCHES SWCON 15 12 0101 SWCON 17 1 Dx SWITCHES CLOSE D5 OPEN OTHER Dx SWITCHES SWCON 3 0 0101 LPTIASWx 3 0 LPTIASWx 8 1 LPTIASW 13 1 VZERO 10mV p p VBIAS 16675 030 16 BIT ADC 160kSPS PGA BUFFER BUFFER AAF DFT MUXSELP_HPTIA_P MUXSELP_HPTIA_N Figure 42 RLOAD02 Measurement Step 4 Measure RCAL via the Impedance Measurement Engine RCAL is a known external f...

Page 161: ...on loop D node P node and RCAL0 pin are shorted by setting the Dx switch and Px switch to close the DR0 and PR0 switches SWCON Bits 7 0 0x11 Other Dx switches and Px switches are open The ac excitation loop N node high speed TIA T node and RCAL1 pin are shorted by setting the Nx switches and Tx switches to close the NR1 and TR1 switches SWCON Bits 15 8 0x85 Close T9 to select RTIA02 SWCON Bit 17 1...

Page 162: ...refore 02 02 RLOAD RLOAD V s Z I s 15 Therefore based on Step 2 through Step 4 02 02 02 02 02 02 02 02 02 02 1 1 RE RE RLOAD RLOAD RE RLOAD RLOAD CAL CAL RE RLOAD RLOAD RLOAD RE RLOAD CAL CAL RE RLOAD RLOAD V s V s Z Z Z I s I s I s Z I s I s I s I s I s Z I s I s 16 If ZCAL magnitude 200 Ω and ZCAL phase 0 it is possible to obtain the following equations 02 02 02 02 02 02 200 RLOAD RE RLOAD RE RE...

Page 163: ... memory DMA OVERVIEW The DMA controller has 20 channels in total The 20 channels are dedicated to managing DMA requests from specific peripherals Channels are assigned as shown in Table 188 Table 188 DMA Channel Assignment Channel Number Peripheral Description 0 SPI1 transmit 1 SPI1 receive 2 3 6 7 13 14 Reserved 4 SPI0 transmit 5 SPI0 receive 8 UART0 transmit 9 UART0 receive 10 I2C slave transmit...

Page 164: ...el control data structures located in the system memory to perform data transfers DMA capable peripherals when enabled to use the DMA can request the DMA controller for a transfer At the end of the programmed number of DMA transfers for a channel the DMA controller generates a single cycle DMA_DONE interrupt corresponding to that channel The DMA_DONE interrupt indicates the completion of the DMA t...

Page 165: ...corresponding data structure from the system memory into its internal cache Any update to the descriptor in the system memory until the DMA_DONE interrupt is received does not guarantee expected behavior It is recommended that the user not update the descriptor before receiving DMA_DONE Example Code Define DMA Structures To define DMA structures use the following code memset dmaChanDesc 0x0 sizeof...

Page 166: ...D_PTR memory location Word 00 Reserved 01 Reserved 10 Source address increment is word 11 No increment Address remains set to the value contained in the DST_END_PTR memory location 29 28 Reserved Undefined Write as zero 27 26 SRC_INC Source Address Increment The address increment depends on the source data width Byte 00 Source address increment is byte 01 Source address increment is half word 10 S...

Page 167: ...1 Peripheral scatter gather alternate During the DMA transfer process if any error occurs during the data transfer CHNL_CFG is written back to the system memory with the N_MINUS_1 bits updated to reflect the number of transfers yet to be completed When a full DMA cycle is complete the CYCLE_CTRL bits are made invalid to indicate the completion of the transfer DMA PRIORITY The priority of a channel...

Page 168: ...7 14 N transfers for the channel where N is the number of transfers If the number of transfers remaining is zero skip to Step 3 2 A request for the channel is automatically generated The controller arbitrates If the channel has the highest priority the DMA cycle returns to Step 1 3 At the end of the transfer the controller generates an interrupt for the corresponding DMA channel Ping Pong CHNL_CFG...

Page 169: ...g Pong DMA Transfer Peripheral Ping Pong DMA Transfer CHNL_CFG Bits 2 0 011 In this mode if the DMA request is from a peripheral the peripheral must send DMA requests after every data transfer to complete primary or alternate descriptor tasks and the final descriptor must be programmed to use a basic transfer type This mode is shown in Figure 45 TASK A PRIMARY CYCLE_CTRL 011 2R 4 N 6 REQUESTS DMA_...

Page 170: ...ontroller starts a DMA cycle using the alternate data structure After the cycle completes the controller performs another four DMA transfers using the primary data structure The controller continues to alternate between using the primary and alternate data structures until the processor configures the alternate data structure for a basic cycle or the DMA reads an invalid data structure Table 194 d...

Page 171: ... need to intervene in between each task Peripheral scatter gather mode is very similar to memory scatter gather mode except for arbitration and request requirements The MCU generates the corresponding DMA_DONE channel interrupt in the NVIC when the entire scatter gather transaction completes using a basic cycle In peripheral scatter gather mode the controller receives an initial request from a per...

Page 172: ...ers without rearbitration 13 4 N_MINUS_1 Configures the controller to perform N DMA transfers where N is a multiple of four 3 Reserved Undefined Write as 0 2 0 CYCLE_CTRL Set to 110 configures the controller to perform a peripheral scatter gather DMA cycle PRIMARY ALTERNATE NOTES 1 FOR ALL PRIMARY TO ALTERNATE TRANSITIONS THE CONTROLLER DOES NOT ENTER THEARBITRATION PROCESS AND IMMEDIATELY PERFORM...

Page 173: ...d transfers minus 1 for that channel Source Read Address SRC_END_PTR N_MINUS_1 SRC_INC for SRC_INC 0 1 2 Source Read Address SRC_END_PTR for SRC_INC 3 Destination Write Address DST_END_PTR N_MINUS_1 DST_INC for DST_INC 0 1 2 Destination Write Address DST_END_PTR for DST_INC 3 Address Decrement The address decrement can be enabled for source and destination addresses Source address decrement can be...

Page 174: ...is considered to be little endian Data arriving from a peripheral is placed in sequence starting from the LSB of a 32 bit word For example if 16 bytes of data arrive at the SPI as 0x01 start 0x02 0x03 0x04 0x0F 0x10 it is stored by the DMA in memory as follows 04_03_02_01 08_07_06_05 0C_0B_0A_09 10_0F_0E_0D Byte Swap Enabled Byte swap happens on 32 bit data boundaries The transfer size must be a m...

Page 175: ...cycle DMA MASTER ENABLE CFG Bit 0 acts as a soft reset to the DMA controller Any activity in the DMA controller can be performed only when this bit is set to 1 Clearing this bit to 0 clears all cached descriptors within the controller and resets the controller POWER DOWN CONSIDERATIONS Complete all ongoing DMA transfers before powering down the chip to hibernate mode However if the user decides to...

Page 176: ...0x40010034 ALT_CLR Channel primary alternate clear 0x00000000 W 0x40010038 PRI_SET Channel priority set 0x00000000 W 0x4001003C PRI_CLR Channel priority clear 0x00000000 W 0x40010048 ERR_CLR Bus error clear 0x00000000 R W 0x4001004C ERRCHNL_CLR Per channel bus error 0x00000000 R W 0x40010050 INVALIDDESC_CLR Per channel invalid descriptor clear 0x00000000 R W 0x40010800 BS_SET Channel bytes swap en...

Page 177: ...channel primary control data base pointer in the system memory The amount of system memory that must be assigned to the DMA controller depends on the number of DMA channels used and whether the alternate channel control data structure is used This register cannot be read when the DMA controller is in the reset state Table 199 Bit Descriptions for PDBPTR Bits Bit Name Settings Description Reset Acc...

Page 178: ...DMA Channels This register disables DMA requests from peripherals Each bit of the register represents the corresponding channel number in the DMA controller Set the appropriate bit to mask the request from the corresponding DMA channel Bit 0 corresponds to DMA Channel 0 Bit M 1 corresponds to DMA Channel M 1 0x000000 R W 0 When read as 0 requests are enabled for Channel C When written as 0 no effe...

Page 179: ...priate bit when it completes the DMA cycle Set the appropriate bit to disable the corresponding channel Bit 0 corresponds to DMA Channel 0 Bit M 1 corresponds to DMA Channel M 1 0x000000 W 0 No effect Use the EN_SET register to enable the channel 1 Disables Channel C CHANNEL PRIMARY ALTERNATE SET REGISTER Address 0x40010030 Reset 0x00000000 Name ALT_SET The ALT_SET register enables the user to con...

Page 180: ...gure Channel Priority This register enables the user to configure a DMA channel to use the high priority level Reading the register returns the status of the channel priority mask Each bit of the register represents the corresponding channel number in the DMA controller This register returns the channel priority mask status or sets the channel priority to high Bit 0 corresponds to DMA Channel 0 Bi...

Page 181: ...egister is used to read and clear the per channel DMA bus error status The error status is set if the controller encountered a bus error while performing a transfer If a bus error occurs on a channel that channel is automatically disabled by the controller The other channels are unaffected Write 1 to clear bits 0x000000 R W1C 0 When read as 0 no bus error has occurred When written as 0 no effect 1...

Page 182: ...d use the default operation Each bit of the register represents the corresponding channel number in the DMA controller Bit 0 corresponds to DMA Channel 0 Bit M 1 corresponds to DMA Channel M 1 0x000000 W 0 No effect Use the BS_SET register to enable byte swap on Channel C 1 Disables byte swap on Channel C CHANNEL SOURCE ADDRESS DECREMENT ENABLE SET REGISTER Address 0x40010810 Reset 0x00000000 Name...

Page 183: ... destination address of a DMA channel to decrement the address instead of incrementing the address after each access Each bit of the register represents the corresponding channel number in the DMA controller Bit 0 corresponds to DMA Channel 0 Bit M 1 corresponds to DMA Channel M 1 0x000000 R W 0 When read as 0 Channel C destination address decrement is disabled When written as 0 no effect Use the ...

Page 184: ... DATAFIFODMAREQEN Enable Data FIFO DMA Channel 0x1 R W 0 Disable DMA requests for data FIFO 1 Enable DMA requests for data FIFO 11 DATAFIFOEN Data FIFO Enable 0x0 R W 0 FIFO is reset No data transfers may take place Sets the read and write pointers to the default values empty FIFO Status indicates if FIFO is empty 1 Normal operation FIFO is not reset 10 0 Reserved Reserved 0x10 R DATA FIFO READ RE...

Page 185: ...rrors and corrections may be reported as bus errors on the ICode or DCode bus as interrupts or ignored SUPPORTED COMMANDS The following is a summary of the commands supported by the flash controller Read Supported through the ICode and DCode interfaces Write Provided by a keyhole mechanism through memory mapped registers Mass erase Clears all user data and program code Page erase Clears user data ...

Page 186: ...mpted erasures and writes are denied Bus errors are also generated if user code attempts to read the protected range of information space Other read only metadata can be made available to the user within the scope of the information space but it is software defined As such the addresses and data types are not defined by the flash controller Besides the top 128 bytes of protected space the remainde...

Page 187: ...D WrProt REST OF UPPERMOST PAGE IN USER SPACE UPPERMOST PAGE N USER SPACE 64 BITS 16675 035 Figure 52 ADuCM355 Flash Memory Structure Top of Page 64 Address 0x1F800 to 0x1FFFF When writing to these locations the user must always write 0xFFFFFFFF to the reserved locations If the user intends to write to either location at run time ensure that these reserved locations remain all 1s 0xFFFFFFFF If dat...

Page 188: ... during the flash controller initialization stall Reads also stall if the flash controller is already busy performing another command such as writing the flash unless the prefetch buffer satisfies those reads ERASING FLASH The flash controller provides page level granularity when erasing user space through the erase page command Alternatively user code can erase the entirety of user space at once ...

Page 189: ...of time approximately 20 μs to 40 μs BURST WRITES Each 2 kB page of flash memory consists of eight rows of 256 bytes Design constraints for programming the flash IP enable back to back writes within a single row to complete more quickly than the equivalent writes across row boundaries For optimizing writes attempt to write flash memory in aligned blocks of up to 256 bytes For example Row 0 is from...

Page 190: ... first write requires setting up the start address DMA writes reduce the number of APB transactions to two Every pair of KH_DATA0 and KH_DATA1 register writes results in a single flash write command executing and the address automatically incrementing to the next data word Regardless of the value of auto increment DMA writes always increment the address in this manner To perform DMA based writes u...

Page 191: ...tate Write Protection User definable regions of user space can be configured in such a way that the flash controller refuses any attempts to modify them affecting both write and erase commands Write protection can be configured at run time or can be stored in user space metadata to be loaded by the Analog Devices bootloader during device start up Run Time Configuration Write protection is configur...

Page 192: ... correspond to 64 bit data words in the flash memory As such if ECC is enabled the most significant 64 bits including the 32 bit signature word must be written all at once Otherwise the ECC byte is corrupted by the second write If using the flash controller to generate the signature value leave the unused 32 bits paired with the signature word in their erased state 0xFFFFFFFF Otherwise spurious EC...

Page 193: ...n space signature check is described in the Signatures section On any read operation if the ECC engine observes a 1 bit error the error is corrected automatically In this case the 1 bit error is either in the ECC byte itself or in the 64 bit dual word being read by the user If a 2 bit error is observed the ECC engine can only report the detection event 2 bit errors cannot be corrected Depending on...

Page 194: ...M355 processor automatically powers down the flash IP when the device hibernates To support this feature the flash controller operates with the power management unit and delays hibernation until any ongoing flash accesses are completed User code is responsible for reading and evaluating flash status registers prior to entering hibernate mode because status registers are not retained in hibernate m...

Page 195: ...40018018 PAGE_ADDR0 Lower page address 0x00000000 R W 0x4001801C PAGE_ADDR1 Upper page address 0x00000000 R W 0x40018020 KEY Key 0x00000000 W 0x40018024 WR_ABORT_ADDR Write abort address 0xXXXXXXXX R 0x40018028 WRPROT Write protection 0xFFFFFFFF R W 0x4001802C SIGNATURE Signature 0xXXXXXXXX R 0x40018030 UCFG User configuration 0x00000000 R W 0x4001803C ABORT_EN_LO IRQ abort enable lower bits 0x000...

Page 196: ...ed 24 20 Reserved Reserved 0x0 R 19 17 ECCERRCNT ECC Correction Counter This counter keeps track of overlapping ECC 1 bit correction reports When configured to generate IRQs or AHB errors in the event of anECCcorrectionevent thisfieldcountsthenumberofECCcorrectionsthatoccur after the first reported correction The counter remains at full scale when it overflows and clears automatically when clearin...

Page 197: ...de The flash controller automatically wakes the flash when required for another data transaction The user can wake the flash at any time by writing the idle command to the CMD register Flash wake up times vary but are typically approximately 5 μs When possible it is recommended that the user begin waking the flash approximately 5 μs before it is used for performance optimization 0x0 R 5 4 CMDFAIL ...

Page 198: ...ered via the command register There is a slight delay between requesting a command and this bit asserting Watch the CMDCOMP bit rather than this bit when polling for command completion 0x0 R INTERRUPT ENABLE REGISTER Address 0x40018004 Reset 0x40 Name IEN Used to specify when interrupts are generated Table 225 Bit Descriptions for IEN Bits Bit Name Settings Description Reset Access 31 8 Reserved R...

Page 199: ...lash automatically The wake up process takes approximately 5 μs If user code can predict approximately 5 μs ahead of time that the flash is required the user can write an idle command to the CMD register to manually wake the flash An abort command is also respected for waking the device and returns the appropriate status bits indicating that the sleep command was aborted When awoken for any reason...

Page 200: ... Be Written on a Write Command 0xFFFFFFFF R W WRITE UPPER DATA REGISTER Address 0x40018014 Reset 0xFFFFFFFF Name KH_DATA1 This register contains the upper half of 64 bit dual word data to be written to flash Table 229 Bit Descriptions for KH_DATA1 Bits Bit Name Settings Description Reset Access 31 0 VALUE Upper Half of 64 Bit Dual Word Data to Be Written on a Write Command If DMA is enabled this r...

Page 201: ...ded to be confidential information WRITE ABORT ADDRESS REGISTER Address 0x40018024 Reset 0xXXXXXXXX Name WR_ABORT_ADDR This register contains the address of a recently aborted write command This address is only populated if the aborted write command was started If the command is aborted early enough to have no effect on the flash IP this address is not updated Table 233 Bit Descriptions for WR_ABO...

Page 202: ...Signature 0xXXXXXXXX R USER CONFIGURATION REGISTER Address 0x40018030 Reset 0x00000000 Name UCFG User key is required Write to this register to enable user control of DMA and auto increment features When user code has finished accessing this register write arbitrary data to the key register to reassert protection Table 236 Bit Descriptions for UCFG Bits Bit Name Settings Description Reset Access 3...

Page 203: ...ECC Enable Set this bit to enable ECC on user space ECC is enabled on all future flash reads in user space from any address between ECC_CFG Bits 31 8 through the top of user space inclusive When cleared or accessing addresses outside the enabled range the flash controller returns the raw data in response to both ICode and DCode reads of user space No error corrections are made or reported 0x0 R W ...

Page 204: ...n set and requires a user key When set this bit cannot be cleared without resetting the device using a POR or external reset This bit plays a direct role in user space security enforcement When set this bit prevents access to user space DCode reads return bus faults with the data bus 0 ICode reads return bus faults with the data bus 0 APB writes are denied and the flash content is unchanged When s...

Page 205: ...56kB FLASH 8kB DATA SRAM 8kB DATA SRAM 16kB DATA SRAM 16kB DATA SRAM 12kB DATA SRAM INITIALIZATION ADDRESS END ADDRESS 0x0000 0000 0x0003 FFFF 0x1000 0000 0x1000 0FFF 0x1000 1000 0x1000 1FFF 0x1000 2000 0x1000 2FFF 0x1000 3000 0x1000 3FFF 0x1000 4000 0x1000 4FFF 0x1000 5000 0x1000 5FFF 0x1000 6000 0x1000 6FFF 0x1000 7000 0x1000 7FFF 0x2000 0000 0x2000 0FFF 0x2000 1000 0x2000 1FFF 0x2000 2000 0x200...

Page 206: ... 0x20000000 and the stack pointer is set at 0x20002000 The stack is written from 0x20001FFF downward The covered memory region is always retained To reserve a given size for the stack area the user can declare a data array of that desired size ending at Position 0x20001FFF so that the stack is not overwritten by the compiler when allocating new variables SRAM Parity For robustness parity check can...

Page 207: ...banks after exiting hibernate mode as follows Initialize by writing to SRAM_CTL Bit 13 after exiting hibernate mode The SRAM banks that are set to 1 by SRAM_CTL Bits 5 0 are initialized Automatic initialization after hibernate mode There is no write required to SRAM_CTL after hibernate mode To select automatic mode set SRAM_CTL Bit 14 prior to hibernation or initialization The SRAMs selected for i...

Page 208: ... all the accesses are word accesses Because initialization is not required for the cache memory the cache feature is available immediately following hibernate mode There is no initialization time penalty To prevent undesired bus errors ignore any initialization of SRAM Bank 5 when cache is enabled As with cache memory the SRAM banks used as instruction memory do not require any previous initializa...

Page 209: ... Rev B Page 209 of 312 REGISTER SUMMARY CACHE FLCC Table 242 FLCC Register Summary Address Name Description Reset Access 0x40018058 STAT Cache status 0x00000000 R 0x4001805C SETUP Cache setup 0x00000000 R W 0x40018060 KEY Cache key 0x00000000 W ...

Page 210: ...Name SETUP The cache user key is required to enable a write to this location The key is cleared after a write to this register Table 244 Bit Descriptions for SETUP Bits Bit Name Settings Description Reset Access 31 1 Reserved Reserved 0x0000000 R 0 ICEN Instruction Cache Enable 0x0 R W 0 Disabled All AHB accesses take place via flash memory 1 Enabled for AHB accesses CACHE KEY REGISTER Address 0x4...

Page 211: ...ne the current revision of the silicon The automated test equipment ATE test program kernel revisions and unique chip ID number can be read from the read only locations detailed in Table 246 Table 246 Kernel and ATE Test Program Revision Details Address Description Access 0x4074C ATE test program revision 16 bit value R 0x40760 Kernel revision number 16 bit value R 0x40770 Unique 16 byte serial nu...

Page 212: ...n digital die 0x4144 R 0x40002024 CHIPID Chip identifier digital die 0x0284 R 0x40002040 SWDEN Serial wire debug enable 0x6E65 W Table 248 AFE Control Register Summary Address Name Description Reset Access 0x400C0400 ADIID Analog Devices identification analog die 0x4144 R 0x400C0404 CHIPID Chip identification analog die 0x5502 R 0x400C0428 DIE2DIESTA 16 bit scratch register to test interdie commun...

Page 213: ...SWDEN Bits Bit Name Settings Description Reset Access 15 0 VALUE Enable SWD Interface Writing this register with en 0x6E65 or EN 0x4E45 enables the SWD interface Writing this register with rp 0x7072 or RP 0x5052 disables the SWD interface Writes of any other value are ignored This register cannot be modified when written with EN or RP This register is reset by a POR or pin reset but not software o...

Page 214: ...resistor can be enabled by software All input and output pins are functional over the full supply range DVDD 2 8 V to 3 6 V maximum and the GPIO low input voltage VINL and GPIO high input voltage VINH are specified as percentages of the supply as follows VINL 0 25 DVDD maximum 19 VINH 0 6 DVDD minimum 20 The absolute maximum input voltage is DVDD 0 3 V The typical leakage current of the GPIOs conf...

Page 215: ...cepted on the rising or the falling edge Each GPIO pin has a corresponding interrupt register GPxPOL based on the port in which it is grouped The interrupt registers configures the interrupt polarity of each pin When set to 0 an interrupt event latches on a high to low transition on the corresponding pin When set to 1 an interrupt event latches on a low to high transition on the corresponding pin ...

Page 216: ...are cleared by writing 1 to the appropriate GPxINT bit The following is example code to enable BM P1 1 as an input interrupt pADI_GPIO1 PE 0x2 Enable internal pull up resistors on P1 1 pADI_GPIO1 IEN 0x1 Enable P1 1 input path pADI_GPIO1 IENA 0x2 Enable External Interrupt A on P1 11 pADI_GPIO1 POL 0x0 Interrupt on falling edge NVIC_EnableIRQ SYS_GPIO_INTA_IRQn Enable GPIO_INTA interrupt source in ...

Page 217: ...1 20 0x0 UART SOUT pin GP0CON Bits 21 20 0x1 P0 11 UART_SIN GPIO GP0CON Bits 23 22 0x0 UART SIN pin GP0CON Bits 23 22 0x1 GP1 GP1CON Controls These Bits P1 0 SYS_WAKE GPIO GP1CON Bits 1 0 0x0 BM P1 1 GPIO boot GP1CON Bits 3 2 0x0 GPIO GP1CON Bits 3 2 0x1 P1 2 SPI1_CLK GPIO GP1CON Bits 5 4 0x0 SPI1 SCLK GP1CON Bits 5 4 0x1 P1 3 SPI1_MOSI GPIO GP1CON Bits 7 6 0x0 SPI1 MOSI GP1CON Bits 7 6 0x1 P1 4 S...

Page 218: ...input path enable 0x0002 R W 0x40020050 GP1IN GPIO Port 1 registered data input 0xXXXX R 0x40020054 GP1OUT GPIO Port 1 data output 0x0000 R W 0x40020058 GP1SET GPIO Port 1 data output set 0x0000 W 0x4002005C GP1CLR GPIO Port 1 data output clear 0x0000 W 0x40020060 GP1TGL GPIO Port 1 pin toggle 0x0000 W 0x40020064 GP1POL GPIO Port 1 interrupt polarity 0x0000 R W 0x40020068 GP1IENA GPIO Port 1 Inter...

Page 219: ... GPIO port output enable 0x0 R W 0x400C0088 PE AFE GPIO port output pull up and pull down enable 0x2 R W 0x400C008C IEN AFE GPIO port input path enable 0x0 R W 0x400C0090 IN AFE GPIO port registered data input 0x0 R 0x400C0094 OUT AFE GPIO port data output 0x0 R W 0x400C0098 SET AFE GPIO port data output set 0x0 W 0x400C009C CLR AFE GPIO port data output clear 0x0 W 0x400C00A0 TGL AFE GPIO port pi...

Page 220: ...2 CON6 Configuration Bits for Port x 6 See Table 255 R W 11 10 CON5 Configuration Bits for Port x 5 See Table 255 R W 9 8 CON4 Configuration Bits for Port x 4 See Table 255 R W 7 6 CON3 Configuration Bits for Port x 3 See Table 255 R W 5 4 CON2 Configuration Bits for Port x 2 See Table 255 R W 3 2 CON1 Configuration Bits for Port x 1 See Table 255 R W 1 0 CON0 Configuration Bits for Port x 0 See T...

Page 221: ...on Access 15 0 IN Registered Data Input Each bit reflects the state of the GPIO pin R GPIO PORT DATA OUTPUT REGISTERS Address 0x40020014 Reset 0x0000 Name GP0OUT Address 0x40020054 Reset 0x0000 Name GP1OUT Address 0x40020094 Reset 0x0000 Name GP2OUT Table 264 Bit Descriptions for GP0OUT GP1OUT GP2OUT Bits Bit Name Settings Description Access 15 0 OUT Data Output Do not use the bit band alias addre...

Page 222: ... bit band alias addresses for this register W 0 Clearing this bit has no effect 1 Set by user code to invert the corresponding GPIO pin GPIO PORT INTERRUPT POLARITY REGISTERS Address 0x40020024 Reset 0x0000 Name GP0POL Address 0x40020064 Reset 0x0000 Name GP1POL Address 0x400200A4 Reset 0x0000 Name GP2POL Table 268 Bit Descriptions for GP0POL GP1POL GP2POL Bits Bit Name Settings Description Access...

Page 223: ...0 Indicates no interrupt on the corresponding pin 1 When set this bit indicates the corresponding pin interrupt event has been latched To clear this bit and interrupt event write 1 to the same bit Writing 0 has no effect GPIO PORT DRIVE STRENGTH SELECT REGISTERS Address 0x40020034 Reset 0x0000 Name GP0DS Address 0x40020074 Reset 0x0000 Name GP1DS Address 0x400200B4 Reset 0x0000 Name GP2DS Table 27...

Page 224: ...d pull down resistor for that particular pin The bit is cleared to disable the pull up resistor and pull down resistor for each pin 0x0 R W AFE GPIO PORT INPUT PATH ENABLE REGISTER Address 0x400C008C Reset 0x0 Name IEN Table 276 Bit Descriptions for IEN Bits Bit Name Settings Description Reset Access 15 2 Reserved Reserved 0x0000 R W 1 0 IEN Input Path Enable Each bit is set to enable the input pa...

Page 225: ...LEAR REGISTER Address 0x400C009C Reset 0x0 Name CLR Table 280 Bit Descriptions for CLR Bits Bit Name Settings Description Reset Access 15 2 Reserved Reserved 0x0000 R W 1 0 CLR Set Output Low for the AFE Die Port Pins GPIOx PWMx Each bit is set to drive the corresponding GPIO pin low Clearing this bit has no effect 0x0 W AFE GPIO PORT PIN TOGGLE REGISTER Address 0x400C00A0 Reset 0x0 Name TGL Table...

Page 226: ... I2C_SCL ACK BIT ACK BIT STOP BIT SLAVE ADDRESS I2C_SDA MSB LSB LSB DATA 1 1 7 8 8 9 9 2 3 TO 6 2 TO 7 R W 16675 139 Figure 57 Typical I2 C Transfer Sequence The user programs the I2 C bus peripheral address in the I2 C bus system This ID can be modified any time a transfer is not in progress The user can set up to four slave addresses that are recognized by the peripheral The peripheral is implem...

Page 227: ...LSB DATA 1 1 7 8 8 9 9 2 3 TO 6 2 TO 7 R W 16675 042 Figure 59 I2 C Repeated Start Sequence On the slave side an interrupt is generated if enabled in the SCTL register when a repeated start and a slave address are received This sequence is differentiated from receiving a start and slave address by using the start and REPSTART status bits in the SSTAT MMR On the master side the master generates a r...

Page 228: ...it 0 is set a slave transfer sequence is monitored for the device address in Register ID0 Register ID1 Register ID2 or Register ID3 If the device address is recognized the device participates in the slave transfer sequence Note that a slave operation always starts with the assertion of one of three interrupt sources a read request MRXREQ SRXREQ a write request MTXREQ STXREQ or a general call inter...

Page 229: ...a R W bit at the end of the timeout period the slave returns a no acknowledge after the timeout period If the first byte is transmitted correctly in a slave transmit sequence but the transmit FIFO is empty for any subsequent bytes in the same transfer with clock stretch enabled the slave returns the previous transmitted byte at the end of the timeout period Master No Acknowledge When receiving dat...

Page 230: ...the programmed count When this overflow occurs the transfer ends after receiving the next byte When the transaction complete interrupt is received the core disables the master by clearing MCTL Bit 0 I2 C is a master and is transmitting data The software flushes the transmit FIFO by setting STAT Bit 9 and disables the transmit request by clearing MCTL Bit 5 When the transmit request is disabled the...

Page 231: ...ddress byte 0x0000 R W 0x40003024 DIV Serial clock period divisor 0x1F1F R W 0x40003028 SCTL Slave control 0x0000 R W 0x4000302C SSTAT Slave I2 C status error and IRQ 0x0001 R 0x40003030 SRX Slave receive 0x0000 R 0x40003034 STX Slave transmit 0x0000 R W 0x40003038 ALT Hardware general call ID 0x0000 R W 0x4000303C ID0 First slave address device ID 0x0000 R W 0x40003040 ID1 Second slave address de...

Page 232: ...d Reserved Write 0 to this bit 0x0 R W 2 LOOPBACK Internal Loopback Enable It is also possible for the master to loop back a transfer to the slave as long as the device address corresponds otherwise known as external loopback 0x0 R W 0 I2C_SCL and I2C_SDA out of the device are not muxed onto their corresponding inputs 1 I2C_SCL and I2C_SDA out of the device are muxed onto their corresponding input...

Page 233: ...sserts when an acknowledge is not received in response to a data write transfer If MCTL Bit 7 is 1 an interrupt is generated when this bit asserts This bit can drive an interrupt This bit is cleared on a read of the MSTAT register 0x0 RC 6 MBUSY Master Busy This bit indicates that the master state machine is servicing a transaction It is cleared if the state machine is idle or another device has c...

Page 234: ...its If 1 byte is required write 0 If more than 256 bytes are required use the extend bit 0x0 R W MASTER CURRENT RECEIVE DATA COUNT REGISTER Address 0x40003014 Reset 0x0000 Name MCRXCNT Table 288 Bit Descriptions for MCRXCNT Bits Bit Name Settings Description Reset Access 15 8 Reserved Reserved 0x0 R 7 0 COUNT Current Receive Count This register gives the total number of bytes received If 256 bytes...

Page 235: ...the SSTAT Bit 13 asserts 1 Generate interrupt when the SSTAT Bit 13 asserts 11 Reserved Reserved 0x0 R W 10 IENSTX Slave Transmit Request Interrupt Enable 0x0 R W 9 IENSRX Slave Receive Request Interrupt Enable 0x0 R W 8 IENSTOP Stop Condition Detected Interrupt Enable 0x0 R W 7 NACK No Acknowledge Next Communication If this bit is set the next communication is not acknowledged 0x0 R W 6 Reserved ...

Page 236: ... previous start condition and a matching address Cleared by a read of the status register If SCTL Bit 8 in the slave control register is asserted the slave interrupt request asserts when this bit is set This bit can drive an interrupt 0x0 RC 9 8 GCID General ID This bit is cleared when SCTL Bit 4 is set to 1 These status bits are not cleared by a general call reset 0x0 R 00 No general call 01 Gene...

Page 237: ...tches This bit only asserts once for a transfer and is cleared when read if SCTL Bit 5 is asserted 0x1 R W SLAVE RECEIVE REGISTER Address 0x40003030 Reset 0x0000 Name SRX Table 294 Bit Descriptions for SRX Bits Bit Name Settings Description Reset Access 15 8 Reserved Reserved 0x0 R 7 0 SRX Slave Receive Register 0x0 R SLAVE TRANSMIT REGISTER Address 0x40003034 Reset 0x0000 Name STX Table 295 Bit D...

Page 238: ...ddress 0x40003048 Reset 0x0000 Name ID3 Table 300 Bit Descriptions for ID3 Bits Bit Name Settings Description Reset Access 15 8 Reserved Reserved 0x0 R 7 0 ID3 Slave Device ID 3 ID3 Bits 7 1 are programmed with the device ID ID3 Bit 0 is don t care See SCTL Bit 1 to see how this register is programmed with a 10 bit address Take care to avoid I2 C reserved slave addresses with values less than 0x10...

Page 239: ...r Master 0x0 R 0 Cleared when this bit is read 1 Set when master automatic stretch mode has timed out 7 4 SLV Automatic Stretch Mode Control for Slave These bits control automatic stretch mode for slave operation These bits allow the slave to hold the I2C_SCL line low and gain more time to service an interrupt load a FIFO or read a FIFO Use the timeout feature to avoid a bus lockup condition where...

Page 240: ...pty before sending an acknowledge or a no acknowledge for an address byte or before sending data for a data byte Stretching stops when the master transmit FIFO is no longer empty or a timeout occurs As a master receiver the I2C_SCL clock is automatically stretched from the negative edge of I2C_SCL before sending an acknowledge or a no acknowledge when the master receive FIFO is full Stretching sto...

Page 241: ...te is timer controlled Fast mode 3 pin mode The SPI0_MOSI and SPI1_MOSI pins in this mode are bidirectional pins The SPI blocks have an additional DMA feature Each SPI block has two DMA channels that interface with a microDMA controller of the Arm Cortex M3 processor One DMA channel is used for transmitting data and the other is used for receiving data SPI OPERATION In SPI operation CS refers to t...

Page 242: ...ve data is not saved to the receive FIFO Similarly to only receive data and not write data to the transmit FIFO set SPIx_CTL Bit 13 to avoid receiving underrun interrupts from the transmit FIFO Transmit Initiated Transfer For transfers initiated by a write to the transmit FIFO the SPI starts transmitting as soon as the first byte is written to the FIFO irrespective of the configuration in SPIx_IEN...

Page 243: ...chip select of the device Though the master can support up to four chip select output lines only one chip select input is used in slave mode The device as a slave transmits and receives 8 bit data until the transfer is concluded by the deassertion of chip select The SPI transfer protocol diagrams in Figure 61 and Figure 62 illustrate the data transfer protocol for the SPI and the effects of SPIx_C...

Page 244: ... The interrupt occurs when the byte is read from the FIFO and written to the shift register 001 An interrupt occurs after every two bytes that are transmitted 010 An interrupt occurs after every third byte that is transmitted 011 An interrupt occurs after every fourth byte that is transmitted 100 An interrupt occurs after every fifth byte that is transmitted 101 An interrupt occurs after every six...

Page 245: ... channels at the same time by setting the DMA request bits for receive or transmit in the SPIx_DMA register If only the DMA transmit request SPIx_DMA Bit 1 is enabled the receive FIFO overflows during an SPI transfer unless the received data is read by user code in which case an overflow interrupt is generated To avoid generating overflow interrupts set the receive FIFO flush bit or disable the SP...

Page 246: ...r of bytes to be received A SPI_RX dummy read The DMA transfer stops when the appropriate number of clock cycles have been generated All DMA data transfers are 16 bit transfers Program the DMA accordingly For example if 16 bytes of data are to be received over the SPI program the DMA to perform eight 16 bit transfers If 17 bytes are to be received nine 16 bit transfers are required The additional ...

Page 247: ...0000 R W 0x40004028 SPI0_FLOW_CTL Flow control 0x0000 R W 0x4000402C SPI0_WAIT_TMR Wait timer for flow control 0x0000 R W 0x40004034 SPI0_CS_OVERRIDE Chip select override 0x0000 R W 0x40024000 SPI1_STAT Status 0x0800 R 0x40024004 SPI1_RX Receive 0x0000 R 0x40024008 SPI1_TX Transmit 0x0000 W 0x4002400C SPI1_DIV Baud rate selection 0x0000 R W 0x40024010 SPI1_CTL Configuration 0x0000 R W 0x40024014 S...

Page 248: ... identify the end of an SPI data frame 12 CSERR Detected a Chip Select Error Condition 0x0 R W1C 0 Cleared to 0 when a 1 is written to this bit 1 Set when the chip select line is deasserted abruptly even before the full byte of data is transmitted completely This bit causes an interrupt 11 CS Chip Select Status This bit reflects the actual chip select status as seen by the SPI module This bit uses...

Page 249: ... chip select override does not affect this bit 0 IRQ SPI Interrupt Status 0x0 R 0 Cleared to 0 when all SPI interrupt sources are cleared 1 Set when an SPI based interrupt occurs RECEIVE REGISTERS Address 0x40004004 Reset 0x0000 Name SPI0_RX Address 0x40024004 Reset 0x0000 Name SPI1_RX Table 307 Bit Descriptions for SPI0_RX SPI1_RX Bits Bit Name Settings Description Reset Access 15 8 BYTE2 8 Bit R...

Page 250: ...CON Continuous Transfer Enable 0x0 R W 0 Disable continuous transfer Each transfer consists of a single 8 bit serial transfer If valid data exists in the SPIx_TX register a new transfer is initiated after a stall period of one serial clock cycle 1 Enable continuous transfer In master mode the transfer continues until no valid data is available in the transmit FIFO Chip select is asserted and remai...

Page 251: ...e This interrupt can be used to signal the change of SPI transfer direction in read command mode 0x0 R W 0 TXDONE interrupt is disabled 1 TXDONE interrupt is enabled 11 RDY Ready Signal Edge Interrupt Enable This bit enables the SPIx_STAT Bit 15 interrupt whenever an active edge occurs on P0 3 signals If SPIx_FLOW_CTL Bits 1 0 0b10 this bit is set whenever an active edge is detected on the P0 3 si...

Page 252: ...register is only used in master mode Table 312 Bit Descriptions for SPI0_CNT SPI1_CNT Bits Bit Name Settings Description Reset Access 15 FRAMECONT Continue Frame Use this bit in conjunction with the SPIx_CTL Bit 11 and SPIx_CNT Bits 13 0 fields This bit is used to control SPI data framing 0x0 R W 0 When writing to this bit if this bit is cleared the SPI master transfers only one frame of SPIx_CNT ...

Page 253: ...lid byte or half word in the receive FIFO 0010 2 valid bytes or half words in the receive FIFO 0011 3 valid bytes or half words in the receive FIFO 0100 4 valid bytes or half words in the receive FIFO 0101 5 valid bytes or half words in the receive FIFO 0110 6 valid bytes or half words in the receive FIFO 0111 7 valid bytes or half words in the receive FIFO 1000 8 valid bytes or half words in the ...

Page 254: ... 0 to 15 corresponding to 1 to 16 transmit bytes Accepted bytes include all the bytes that must be sent out to the slave such as command and address if required The design does not differentiate between the command and address but transmits the specified number of bytes from the transmit FIFO If there is a latency between the command transmission and data reception account for the number of transm...

Page 255: ...Control Mode Flow control configuration for data reads When the P0 3 signal is used for flow control P0 3 can be any control signal that is tied to this P0 3 input of the SPI module 0x0 R W 00 Flow control is disabled 01 Flow control is based on timer SPIx_WAIT_TMR 10 Flow control is based on P0 3 signal 11 Flow control is based on MISO pin WAIT TIMER FOR FLOW CONTROL REGISTERS Address 0x4000402C ...

Page 256: ...it shift register causes the transmit register empty status flag to be set The receive operation uses the same data format as the transmit configuration except for the number of stop bits which is always one After detection of the start bit the received word is shifted into the internal receive shift register After the appropriate number of bits including stop bits are received the data and any st...

Page 257: ...to the period of four consecutive characters where a single character time is one start bit n data bits one parity bit and one stop bit where n depends on the word length selected by COMLCR Bits 1 0 DMA Mode In DMA mode user code does not move data to and from the UART DMA request signals entering the external DMA block indicate that the UART is ready to transmit or receive data These DMA request ...

Page 258: ...Complete ongoing UART transfers before powering down the chip into hibernate mode Alternatively disable the UART by clearing the COMDIV register to 0x0000 before placing the device into hibernation If hibernate mode is selected while a UART transfer is on the transfer does not continue on a return from hibernation All the intermediate data states and status logic in the UART are cleared However th...

Page 259: ...4 COMLSR Line status 0x0060 RC 0x40005018 COMMSR Modem status 0x0000 RC 0x4000501C COMSCR Scratch buffer 0x0000 R W 0x40005020 COMFCR FIFO control 0x0000 R W 0x40005024 COMFBR Fractional baud rate 0x0000 R W 0x40005028 COMDIV Baud rate divider 0x0000 R W 0x4000502C COMLCR2 Second line control 0x0002 R W 0x40005030 COMCTL UART control 0x0100 R W 0x40005034 COMRFC Receive FIFO count 0x0000 R 0x40005...

Page 260: ...eceived data If COMIEN Bit 0 is set an interrupt generates when this register is fully loaded with the received data via the serial input port If user code sets the COMIEN Bit 0 while COMRX is full an interrupt generates immediately 0x0 R INTERRUPT ENABLE REGISTER Address 0x40005004 Reset 0x0000 Name COMIEN COMIEN is the interrupt enable register that configures which interrupt source generates th...

Page 261: ...eration 5 SP Stick Parity Used to force parity to defined values When set the parity is based on the following bit settings When EPS 1 and PEN 1 the parity is forced to 0 When EPS 0 and PEN 1 the parity is forced to 1 When EPS X and PEN 0 no parity is transmitted 0x0 R W 0 Parity is not forced based on EPS and PEN 1 Parity forced based on EPS and PEN 4 EPS Parity Select This bit only has meaning i...

Page 262: ...Byte s in Receive FIFO have Parity Error Frame Error or Break Indication Only used in 16550 UART mode This bit is cleared if there are no more errors in the receive FIFO 0x0 RC 6 TEMT COMTX and Shift Register Empty Status 0x1 R 0 COMTX has been written to and contains data to be transmitted Take care not to overwrite its value 1 COMTX and the transmit shift register are empty and it is safe to wri...

Page 263: ...lears after COMMSR is read 0x0 R 0 DSR has not changed state since COMMSR was last read 1 DSR changed state since COMMSR was last read 0 DCTS Delta CTS If set this bit self clears after COMMSR is read 0x0 R 0 CTS has not changed state since COMMSR was last read 1 CTS changed state since COMMSR was last read SCRATCH BUFFER REGISTER Address 0x4000501C Reset 0x0000 Name COMSCR Table 329 Bit Descripti...

Page 264: ...BAUD RATE REGISTER Address 0x40005024 Reset 0x0000 Name COMFBR Table 331 Bit Descriptions for COMFBR Bits Bit Name Settings Description Reset Access 15 FBEN Fractional Baud Rate Generator Enable The generating of fractional baud rate and the final baud rate of UART operation are calculated using the following 0x0 R W Baud Rate UCLK 2 M N 2048 16 COMDIV 14 13 Reserved Reserved 0x0 R 12 11 DIVM Frac...

Page 265: ...its Bit Name Settings Description Reset Access 15 5 Reserved Reserved 0x0 R 4 0 RFC Current Receive FIFO Data Bytes 0x0 R TRANSMIT FIFO COUNT REGISTER Address 0x40005038 Reset 0x0000 Name COMTFC Table 336 Bit Descriptions for COMTFC Bits Bit Name Settings Description Reset Access 15 5 Reserved Reserved 0x0 R 4 0 TFC Current Transmit FIFO Data Bytes 0x0 R RS485 HALF DUPLEX CONTROL REGISTER Address ...

Page 266: ...dge 110 Seventh edge 111 Eighth edge 3 Reserved Reserved 0x0 R 2 TOIEN Enable Time Out Interrupt 0x0 R W 1 DNIEN Enable Done Interrupt 0x0 R W 0 ABE Autobaud Enable 0x0 R W AUTOBAUD STATUS LOW REGISTER Address 0x40005044 Reset 0x0000 Name COMASRL Table 339 Bit Descriptions for COMASRL Bits Bit Name Settings Description Reset Access 15 4 CNT 11 0 Autobaud Counter Value 0x0 R 3 NEETO Timed Out Due t...

Page 267: ...ult owing to the synchronization period required The CON0 register selects the timer mode configures the clock source selects count up or count down starts the counter and controls the event capture function An interrupt signal is generated each time the value of the counter reaches 0 when counting down or each time the counter value reaches the maximum value when counting up Clear an IRQ by writi...

Page 268: ...e returning from the interrupt handler Use the data synchronization barrier DSB instruction if necessary and check that GPTx_STAT Bit 7 0 as follows __asm void asmDSB nop DSB BX LR The value of a counter can be read at any time by accessing its value register GPTx_CURCNT In an asynchronous configuration GPTx_CURCNT must always be read twice If the two readings are different this register must be r...

Page 269: ... 1000 Reserved Reserved Reserved 1001 GPIO Interrupt A Reserved Reserved 1010 GPIO Interrupt B Reserved Reserved 1011 General Purpose Timer 1 Reserved Reserved 1100 General Purpose Timer 1 SYS_WAKE Reserved 1101 Flash controller Reserved Reserved 1110 Reserved General Purpose Timer 0 Reserved 1111 Reserved General Purpose Timer 2 Reserved General Purpose Timers Power Gating To limit power consumpt...

Page 270: ... 16 bit synchronous load value 0x0000 R W 0x40000404 GPT1_CURCNT 16 bit timer synchronous value 0x0000 R 0x40000408 GPT1_CTL Control 0x000A R W 0x4000040C GPT1_CLRINT Clear interrupt 0x0000 W 0x40000410 GPT1_CAPTURE Capture 0x0000 R 0x40000414 GPT1_ALOAD 16 bit asynchronous load value 0x0000 R W 0x40000418 GPT1_ACURCNT 16 bit timer asynchronous value 0x0000 R 0x4000041C GPT1_STAT Status 0x0000 R 0...

Page 271: ...PT2_CTL Table 345 Bit Descriptions for GPT0_CTL GPT1_CTL GPT2_CTL Bits Bit Name Settings Description Reset Access 15 SYNCBYP Synchronization Bypass Used to bypass the synchronization logic within the block Use only when both the general purpose timer and the CPU are clocked from the same source 0x0 R W 14 Reserved Reserved 0x0 R 13 EVTEN Event Select Used to enable and to disable the capture of ev...

Page 272: ...or divide by 4 if SYNCBYP 0 01 Source clock 16 10 Source clock 64 11 Source clock 256 CLEAR INTERRUPT REGISTERS Address 0x4000000C Reset 0x0000 Name GPT0_CLRINT Address 0x4000040C Reset 0x0000 Name GPT1_CLRINT Address 0x4000080C Reset 0x0000 Name GPT2_CLRINT Table 346 Bit Descriptions for GPT0_CLRINT GPT1_CLRINT GPT2_CLRINT Bits Bit Name Settings Description Reset Access 15 2 Reserved Reserved 0x0...

Page 273: ...d GPTx_CTL Bits 6 5 00 or if the high frequency oscillator is clocking both the timer and CPU directly 0x0000 R STATUS REGISTERS Address 0x4000001C Reset 0x0000 Name GPT0_STAT Address 0x4000041C Reset 0x0000 Name GPT1_STAT Address 0x4000081C Reset 0x0000 Name GPT2_STAT Table 350 Bit Descriptions for GPT0_STAT GPT1_STAT GPT2_STAT Bits Bit Name Settings Description Reset Access 15 8 Reserved Reserve...

Page 274: ...s a dedicated PWM output feature The high period for the PWM is the difference between the values in the timer load register and either the PWMMAT0 register or PWMMATCH register The low period for the PWM is the difference between either the PWMMAT0 register or PWMMATCH register and the overflow value 0xFFFF Increasing and reducing the load value increases and reduces the frequency of the PWM outp...

Page 275: ...nous 0x0000 R 0x400C0D1C STA0 Status 0x0000 R 0x400C0D20 PWMCON0 PWM control 0x0000 R W 0x400C0D24 PWMMAT0 PWM match value 0x0000 R W 0x400C0D28 INTEN Interrupt enable 0x0000 R W Table 352 AGPT1 Register Summary Address Name Description Reset Access 0x400C0E00 LOAD 16 bit load value 0x0000 R W 0x400C0E04 CURCNT 16 bit timer value 0x0000 R 0x400C0E08 CTL Control 0x000A R W 0x400C0E0C CLRINT Clear i...

Page 276: ... 16 bit counter and 8 bit prescale are reset This reset is required in PWM demodulation mode 0x0 R W 13 EVTEN Event Select Used to enable and disable the capture of events Used in conjunction with the event select range When a selected event occurs the current value of the up or down counter is captured in GPTx_CAPTURE 0x0 R W 0 Events are not captured 1 Events are captured 12 8 EVENT Event Select...

Page 277: ...terrupt 0 No effect 0 TMOUT Clear Timeout Interrupt This bit is used to clear a timeout interrupt 0x0 W1C 1 Clears the timeout interrupt 0 No effect 16 BIT LOAD VALUE ASYNCHRONOUS REGISTER Address 0x400C0D14 Reset 0x0000 Name ALD0 Only use when a synchronous clock source is selected CON0 Bits 6 5 00 Table 357 Bit Descriptions for ALD0 Bits Bit Name Settings Description Reset Access 15 0 ALOAD Load...

Page 278: ... Event Pending A capture of the current timer value has occurred 0x0 R 0 No capture event is pending 1 A capture event is pending 0 TMOUT Timeout Event Occurred This bit is set automatically when the value of the counter reaches zero while counting down or reaches full scale when counting up This bit is cleared when CLRI0 Bit 0 is set by the user 0x0 R 0 No timeout event has occurred 1 A timeout e...

Page 279: ... value Value delayed two PCLK cycles due to clock synchronizers 0x0 R CONTROL REGISTER Address 0x400C0E08 Reset 0x000A Name CTL Table 365 Bit Descriptions for CTL Bits Bit Name Settings Description Reset Access 15 SYNCBYP Synchronization Bypass Used to bypass the synchronization logic within the block Use only with synchronous clocks This bit field also changes the PRE bit maximum prescaler count ...

Page 280: ...1 0 PRE Prescaler Controls the prescaler division factor applied to the selected clock of the timer 0x2 R W 00 Source clock 1 or source clock 4 When CTL Bit 15 is set source clock 1 When cleared source clock 4 01 Source clock 16 10 Source clock 64 11 Source clock 256 CLEAR INTERRUPT REGISTER Address 0x400C0E0C Reset 0x0000 Name CLRINT Table 366 Bit Descriptions for CLRINT Bits Bit Name Settings De...

Page 281: ...ite to CTL is still crossing into the timer clock domain Check this bit after writing CTL and suppress further writes until this bit is cleared 0x0 R 0 Timer ready to receive commands to control register 1 Timer not ready to receive commands to control register 5 1 Reserved Reserved 0x0 R 0 TIMEOUT Timeout Event Occurred This bit is set automatically when the value of the counter reaches zero whil...

Page 282: ...f the timer When the watchdog timer is not enabled the watchdog timer can be reconfigured at any time When the watchdog timer decrements to 0 a reset is generated This reset can be prevented by writing 0xCCCC to the WDTCLRI register Writing 0xCCCC to WDTCLRI causes the watchdog timer to reload with the watchdog timer configuration in free running mode In this case the watchdog timer immediately be...

Page 283: ...mary Address Name Description Reset Access 0x400C0900 WDTLD Watchdog timer load value 0x1000 R W 0x400C0904 WDTVALS Current count value 0x1000 R 0x400C0908 WDTCON Watchdog timer control 0x00C9 R W 0x400C090C WDTCLRI Refresh watchdog 0x0000 W 0x400C0918 WDTSTA Timer status 0x0000 R 0x400C091C WDTMINLD Minimum load value 0x0800 R W ...

Page 284: ...ut or if a refresh occurs within WDTMINLD 1 Enable Debug feature An interrupt occurs instead of a reset if the counter times out or if a refresh occurs within WDTMINLD 9 MINLOAD_EN Timer Window Control When enabled if the user refreshes the timer before the counter reaches the value in the WDTMINLD register a reset or IRQ occurs 0x1 R W 0 Disable Disable window feature Watchdog is refreshed if use...

Page 285: ...LD WDTMINLD Register Write Status 0x0 R 0 The WDTMINLD value is fully updated Arm and AFE watchdog clock domains and the WDTMINLD values match 1 WDTMINLD value update in progress Arm peripheral bus and the WDTMINLD value are being synchronized to the 32 kHz clock domain 5 Reserved Reserved 0x0 R 4 LOCK Lock Status 0x0 R 0 Timer operation not locked 1 Timer enabled and locked Set automatically in h...

Page 286: ...et 0x0800 Name WDTMINLD Watchdog timer minimum timeout period Lower window limit Table 378 Bit Descriptions for WDTMINLD Bits Bit Name Settings Description Reset Access 15 0 MIN_LOAD WDT Minimum Load Value If software writes to WDTCLRI before the counter reaches the MIN_LOAD value a WDT reset or IRQ occurs 0x800 R W ...

Page 287: ...e CPU The snapshot is persistent and is only overwritten when the CPU issues a request to capture a new value REGULAR AND PERIODIC MODULO 60 INTERRUPTS To enable periodic interrupts the modulo 60 feature of the timer can be used The modulo block divides the timer counter by 60 if the remainder modulus equals the value in CR0 Bits 10 5 or a modulo alarm or interrupt occurs To enable periodic interr...

Page 288: ...when power is restored to the processor To facilitate this interrupt the timer sends a 32 kHz timed version of the same interrupt to the wake up controller in the PMU which causes the digital core to be repowered When the CPU is woken up it can inspect both the PMU and WUT to understand the cause of the interrupt event for the wakeup WUT Capacity to Accommodate Posted Writes by CPU If a posted wri...

Page 289: ...eued and executing posted writes in the WUT Cancellation is achieved by writing a cancellation key of 0xA2C5 to the GWY register which takes immediate effect These actions maintain the integrity of the always on half of the WUT Do not post any further register writes to the WUT until power is lost by the core to ensure that no communication between the CPU and the WUT occurs Such communication mak...

Page 290: ...x4000140C CNT0 Count 0 0x0000 R W 0x40001410 CNT1 Count 1 0x0000 R W 0x40001414 ALM0 Alarm 0 0xFFFF R W 0x40001418 ALM1 Alarm 1 0xFFFF R W 0x40001420 GWY Gateway 0x0000 W 0x40001428 CR1 Control 1 0x01E0 R W 0x4000142C SR2 Status 2 0xC000 R W 0x40001430 SNAP0 Snapshot 0 0x0000 R 0x40001434 SNAP1 Snapshot 1 0x0000 R 0x40001438 SNAP2 Snapshot 2 0x0000 R 0x4000143C MOD Modulo 0x0040 R 0x40001440 CNT2 ...

Page 291: ... interrupt source in the SR0 status register When power loss is imminent to all power domains on the device apart from the WUT the WUT activates its isolation barrier so that the WUT can continue to operate independently of the core When power is subsequently restored to the rest of the device the WUT activates the ISOINT interrupt source to act as a sticky record of the power loss event just fini...

Page 292: ...ster SR0 0x0 R W 0 Disable detection of alarm events 1 Enable detection of alarm events 0 CNTEN Global Enable for the WUT CNTEN enables counting of elapsed real time and acts as a master enable for the WUT If the WUT is enabled by activating CNTEN this event causes a realignment of the prescaler and the Modulo 60 counter used by the WUT to generate MOD60ALMINT sourced interrupts in SR0 0x0 R W 0 D...

Page 293: ...room in the CPU to post a new write transaction to a 32 kHz sourced MMR or MMR bit field in the RTC To enable a WPENDINT interrupt set WPENDINTEN to 1 in the CR0 register Cleared by writing a value of one to this bit 0x0 R W1C 0 There has been no change in the pending status of any posted write transaction in the WUT since WPENDINT was last cleared 1 A posted write transaction has been dispatched ...

Page 294: ... this bit was last cleared by the CPU 1 An ALMINT interrupt event has occurred since this bit was last cleared by the CPU 0 Reserved Reserved 0x0 R STATUS 1 REGISTER Address 0x40001408 Reset 0x0078 Name SR1 Table 382 Bit Descriptions for SR1 Bits Bit Name Settings Description Reset Access 15 13 Reserved Reserved 0x0 R 12 WPNDALM1 Pending Status of Posted Writes to the ALM1 Register WPNDALM1 indica...

Page 295: ... CNT1 can be written in any order but paired twin writes must be carried out by the CPU to have any effect on the WUT count A paired write to CNT0 and CNT1 in any order zeroes the prescaler in the WUT and thus causes a redefinition of elapsed time by the CPU to align exactly with newly created modulo 1 and modulo 60 boundaries Such a redefinition also causes the WUT to create a trim boundary and i...

Page 296: ... are active in the CR0 register Table 386 Bit Descriptions for ALM1 Bits Bit Name Settings Description Reset Access 15 0 VALUE Upper 16 Prescaled Nonfractional Bits of the WUT Alarm Target Time The alarm register has a different reset value to the WUT count to avoid spurious alarms 0xFFFF R W GATEWAY REGISTER Address 0x40001420 Reset 0x0000 Name GWY GWY is a gateway MMR address through which the C...

Page 297: ... 22 4 0011 Prescale the WUT base clock by 23 8 0100 Prescale the WUT base clock by 24 16 0101 Prescale the WUT base clock by 25 32 0110 Prescale the WUT base clock by 26 64 0111 Prescale the WUT base clock by 27 128 1000 Prescale the WUT base clock by 28 256 1001 Prescale the WUT base clock by 29 512 1010 Prescale the WUT base clock by 210 1024 1011 Prescale the WUT base clock by 211 2048 1100 Pre...

Page 298: ...MMR can be accepted at this time 0x0 R 0 Results of a posted write to CR1 are not yet visible by the CPU 1 Results of a posted write to CR1 are visible by the CPU 12 WPNDCR1MIR Pending Status of Posted Writes to CR1 This bit indicates if a posted register write to CR1 is currently pending and awaiting execution meaning that no further write to the same MMR can be accepted at this time 0x0 R 0 The ...

Page 299: ...time unit and the advancement of the WUT count is activated For PSINT to cause an interrupt from the RTC the corresponding enable bit for the interrupt fan in the PSINTEN bit in CR1 must be active high This interrupt source is cleared by writing 1 Full interrupt capability is available for RTC1 0x0 R W1C 0 The prescaled gated clock for the WUT count in CNT1 CNT0 and CNT2 has not activated since th...

Page 300: ...aled WUT time units past the most recent modulo 60 roll over event A roll over is a synonym for a modulo 60 boundary The WUT realigns itself to create coincident modulo 60 and modulo 1 boundaries whenever either of the following events occurs CPU writes a new pair of values to the CNT1 and CNT0 registers to redefine the elapsed time units count while the WUT is enabled and this posted twin write i...

Page 301: ...by CNT1 CNT0 and CNT2 The overall resolution of the real time count including the fractional bits in CNT2 is therefore one 32 kHz clock period CNT2 is zeroed during the CPU writes a new pair of values to the CNT1 and CNT0 registers to redefine the elapsed time units count while the WUT is enabled and this posted twin write is executed when the CPU enables the WUT from a disabled state using the CN...

Page 302: ... CNTx gives an overall 47 bits of the WUT count that belong together and are coherent with each other even though the actual continuing value of CNT2 CNT1 and CNT0 keeps advancing while the WUT counts real time This bit both indicates the sequence number in the triple read and acts a read data select for the value returned when CNTx is read Normally this bit keeps advancing by one starting from 0b...

Page 303: ...CRC RESULT CRC CONTROL CRC INPUT DATA MIRROR OPTIONS APB INTERFACE CRC COMPUTATION 16675 156 Figure 66 CRC Block Diagram CRC Architectural Concepts The CRC accelerator works on 32 bit data words which are either fed to the block through the DMA channel dedicated to the CRC accelerator or directly by the MCU The CRC accelerator guarantees immediate availability of the CRC output CRC Operating Modes...

Page 304: ... is detailed in Table 397 Table 397 16 Bit Polynomial Programming Register Format MSB First Calculation Register Bit s Value CRC Polynomial Register POLY 31 24 0001 0000 23 16 0010 0001 15 8 0x08B0 7 0 0x08B0 CRC Result Register Result 31 24 CRC 23 16 Result 15 8 0x08B0 7 0 0x08B0 Initial Seed Programmed in CRC Result Register Result 31 24 CRC 23 16 Seed 15 8 0x08B0 7 0 0x08B0 16 Bit Polynomial Pr...

Page 305: ...t Calculation Polynomial CRC 8 ATM x8 x2 x 1 1000 0011 1 0x83 where the smallest exponent x0 term is implied Therefore the polynomial is 1000 0011 When right justified in the polynomial register the register format is detailed in Table 400 Table 400 8 Bit Polynomial Programming Register Format LSB First Calculation Register Bit s Value CRC Polynomial Register POLY 31 24 0x08B0 23 16 0x08B0 15 8 0x...

Page 306: ... writing into the IPDATA register The CRC accelerator continues to calculate the CRC as long as data is written to the IPDATA register It is the responsibility of the application to count the number of words written to the CRC block After all the words are written the application can read the result register 4 Read the result register This register contains the x bit result in x MSB bits for MSB f...

Page 307: ...ng of the data The serial engine calculates CIN Bits 31 0 starting with the MSB bit and ending with LSB bit in sequence CIN Bit 31 to CIN Bit 0 in descending order Table 403 Mirroring Options for 32 Bit Input Data with 32 Bit Polynomial W16SWP BYTMIRR BITMIRR Input Data DIN Bits 31 0 CRC Input Data CIN Bits 31 0 0 0 0 DIN Bits 31 0 CIN Bits 31 0 DIN Bits 31 0 0 0 1 DIN Bits 31 0 CIN Bits 31 0 DIN ...

Page 308: ...n Reset Access 0x40040000 CTL CRC control register 0x10000000 R W 0x40040004 IPDATA Input data word register 0x00000000 W 0x40040008 RESULT CRC result register 0x00000000 R W 0x4004000C POLY Programmable CRC polynomial 0x04C11DB7 R W 0x40040010 to 0x40040017 IPBITSN Input data bits 0x00 for 8 bytes W 0x40040010 IPBYTE Input data byte 0x00 W ...

Page 309: ... W 0 Bit mirroring is disabled 1 Bit mirroring is enabled 1 LSBFIRST LSB First Calculation Order 0x0 R W 0 MSB first CRC calculation 1 LSB first CRC calculation 0 EN CRC Peripheral Enable 0x0 R W 0 CRC peripheral is disabled 1 CRC peripheral is enabled INPUT DATA WORD REGISTER Address 0x40040004 Reset 0x00000000 Name IPDATA Table 406 Bit Descriptions for IPDATA Bits Bit Name Settings Description R...

Page 310: ...A_BITS Input Data Bits These fields are used to calculate CRC data byte from 1 bit to 7 bits of input data Computing CRC on x bits of input data can be achieved by writing the byte to Bit x of this register 0x0 W INPUT DATA BYTE REGISTER Address 0x40040010 Reset 0x00 Name IPBYTE Table 410 Bit Descriptions for IPBYTE Bits Bit Name Settings Description Reset Access 7 0 DATA_BYTE Input Data Byte Writ...

Page 311: ...OR SOCKET CE0 RE0 SE0 470nF RC0_0 DVDD AGND CAP_POT0 100nF VBIAS0 RESET DGND DVDD_REG 470nF DVDD_REG_AD 470nF 30pF 30pF 30pF VBAT 4 7µF 100nF 1R6 BEAD 1R6 BEAD 100nF 100nF POWER SUPPLY BM P1 1 VBAT 10MΩ AGND AIN0 AIN1 TEMPSENSOR RELATIVE HUMIDITY SENSOR DVDD AVDD VBAT TVS DIODE ARRAY AVDD_DD AVDD AGND_DD RCAL0 RCAL1 200Ω AIN4_LPF0 4 7µF DVDD 100nF DVDD 100nF 100nF 100nF 100nF INTERFACE BOARD CONNE...

Page 312: ... discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality LegalTermsandConditions Information furnished by Analog Devices i...

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