Chapter 2
Channel Operation
M4K708 Module: User’s Manual
page 2 - 9
Read
The Channel Status register provides various channel status bits and is initialized
to 0001 (H) at reset
.
Write/
Read
Setting a bit of the Channel Interrupt Mask register enables the corresponding
channel interrupt.
Initialized to 0000 (H) at reset.
2.3.4
Channel Status Register
Address:
xx006 (H)
Bit Bit
Name
Description
05–15
Reserved
Set to 0
04
HCB
Channel FIFO Counter bit 16 [see
Channel FIFO
Counter Register,
page 2-11]
03
ITX
Channel in Transmit (Tx mode)
0 = Channel not transmitting
1 = Channel is in Transmit state
02
FUL
Channel FIFO full (Tx mode)
0 = Bit not active
1 = FIFO full (65536 16-bit Words)
01
HFL
Channel FIFO half full (Tx and Rx mode)
0 = Bit not active
1 = FIFO half full (more than 32768 16-bit Words)
00
EMT
Channel FIFO empty (Rx mode)
0 = Bit not active
1 = FIFO empty (0 Words)
Channel Status Register
2.3.5
Channel Interrupt Mask Register
Address:
xx008 (H)
Bit Bit
Name
Description
02–15
Reserved
Set to 0
01
WOM
Word Over Mask
0 = Disable WOV bit interrupt
1 = Enable WOV bit interrupt
00
FOM
FIFO Over Mask
0 = Disable FOV bit interrupt
1 = Enable FOV bit interrupt
Channel Interrupt Mask Register
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