Chapter 2
Channel Operation
M4K708 Module: User’s Manual
page 2 - 11
Write/
Read
The user sets the Channel Event Frequency Register to the number of ARINC 708
Words to be sent/received between interrupts/triggers.
Read
The user reads the Channel FIFO Counter register in order to know the exact
quantity of words currently residing within the channel’s FIFO. Each write to the
FIFO the counter is incremented by 1 and each read it is decremented by 1. The
counter is initialized to 0000(H) at reset. While in Continuous FIFO Retransmit
mode the counter holds a fixed value with the number of words written to the FIFO
before start.
Write/
Read
Setting a bit of the Channel Output Trigger Mask register enables the
corresponding trigger condition to send a pulse over the OUTRIGn output pin (see
3.3.1.1 Module Terminal Stick Pin Assignments And Description
on page 3-4).
The register is initialized to 0000(H) at reset.
See
Channel Interrupt Status Register,
page 2-10.
2.3.8
Channel Event Frequency Register
Address:
xx00E (H)
Bit
Bit Name
Description
10-15
Reserved
Set to 0
00-09
Intrpt_Intrvl
Number of 708 Words to be sent/received between interrupts.
Transmit: maximum value = 655
Receive: maximum value = 636
Minimum value = 1
Set to ‘1’ upon power-up or reset
Channel Event Frequency Register
2.3.9
Channel FIFO Counter Register
Address:
xx010 (H)
Bit
Bit Name
Description
00-15
FIFO_Cntr
Number of words residing within the FIFO. Bit 16 of
this counter resides at bit 04 within the Channel
Status register. It is active for one value only when
the FIFO is full to represent 65536 [10000 H].
Channel FIFO Counter
2.3.10 Channel Output Trigger Mask Register
Address:
xx012 (H)
Bit
Bit Name
Description
02-15
Reserved
01
TWOM
Trigger Word Over Mask
0 = Disable WOV bit condition
1 = Enable WOV bit condition
00
TFOM
Trigger FIFO Over Mask
0 = Disable FOV bit condition
1 = Enable FOV bit condition
Channel Output Trigger Mask
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