Chapter 2
Channel Operation
page 2 - 10
Excalibur Systems
Read
Each bit in the Channel Interrupt Status register indicates the corresponding
interrupt status. These bits will be set regardless of the state of the Channel
Interrupt Mask register bits.
Initialized to 0000 (H) at reset.
Note:
After receipt of an interrupt, the user must reset the interrupt condition bit
via the
Channel Interrupt Clear Register
Write
Writing to the Channel Interrupt Clear Register clears the corresponding Channel
Interrupt Status register bit.
.
2.3.6
Channel Interrupt Status Register
Address:
xx00A (H)
Bit
Bit Name
Description
02–15
Reserved Set
to
0
01
WOV
Word Over [Tx/Rx Interrupt]
0 = Bit not active
1 = Number of 708 Words, set in the
Channel
Event Frequency Register
, were
transmitted/received.
00
FOV
FIFO Over [Error Interrupt]
0 = Bit not active
1 = All Words in channel were transmitted and the
FIFO is empty (in Continuous mode) in Tx
mode or the FIFO reached full state in Rx
mode.
Channel Interrupt Status Register
2.3.7
Channel Interrupt Clear Register
Address:
xx00C (H)
Bit
Bit Name
Description
02–15
Reserved
Set to 0
01
WOC
Word Over Clear
0 = Bit not active
1 = Clear WOV bit interrupt
00
FOC
FIFO Over Clear
0 = Bit not active
1 = Clear FOV bit interrupt
Channel Interrupt Clear Register
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com