DRQ[7::5], DRQ[3::0] (I)
DMA Requests DRQ[7::5] and DRQ[3::0] are asynchronous channel requests
used by peripheral devices and the I/O channel microprocessors to gain DMA
service (or control of the system). They are prioritized, with DRQ0 having the
highest priority and DRQ7 having the lowest. A request is generated by
bringing a DRQ line to an active level. A DRQ line must be held high until the
corresponding DMA Request Acknowledge (DAK) line goes active. DRQ[3::0]
will perform 8-bit DMA transfers; DRQ[7::5] will perform 16-bit transfers.
IO16# (I)
I/O 16-bit Chip Select (IO16#) signals the system board that the present data
transfer is a 16-bit, 1 wait-state, I/O cycle. It is derived from an address decode.
IO16# is active low and should be driven with an open collector or tri-state
driver capable of sinking 20 mAmps.
IOCHK# (I)
I/O Channel Check (IOCHK#) provides the system board with parity (error)
information about memory or devices on the I/O channel. When this signal is
active, it indicates an uncorrectable system error.
IORC# (I/O)
I/O Read (IORC#) instructs an I/O device to drive its data onto the data bus.
It may be driven by the system microprocessor or DMA controller, or by a
microprocessor or DMA controller resident on the I/O channel. This signal is
active low.
IOWC# (I/O)
I/O Write (IOWC#) instructs an I/O device to read the data on the data bus. It
may be driven by any microprocessor or DMA controller in the system. This
signal is active low.
IRQ[15::14], IRQ[12::9], IRQ[7::3] (I)
Interrupt Requests IRQ[15::14], IRQ[12::9] and IRQ[7::3] are used to signal
the microprocessor that an I/O device needs attention. The interrupt requests
are prioritized, with IRQ[15::14] and IRQ[12::9] having the highest priority
(IRQ9 is the highest) and IRQ[7::3] having the lowest priority (IRQ7 is the
lowest). An interrupt request is generated when an IRQ line is raised from low
to high. The line must be held high until the microprocessor acknowledges
the interrupt request (Interrupt Service routine).
LA[23::17] (I/O)
These signals (unlatched) are used to address memory and I/O devices within
the system. They give the system up to 16MB of addressability. These signals
are valid when BALE is high. LA[23::17] are not latched during microprocessor
cycles and therefore do not stay valid for the whole cycle. Their purpose is to
generate memory decodes for 1 wait-state memory cycles. These decodes
should be latched by I/O adapters on the falling edge of BALE. These signals
ISA REFERENCE
TECHNICAL REFERENCE
2-5
Summary of Contents for SB586TCP/166
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Page 11: ...SPECIFICATIONS TECHNICAL REFERENCE 1 3...
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Page 94: ...This page intentionally left blank ADVANCED SETUP 5 18 TECHNICAL REFERENCE...
Page 106: ...This page intentionally left blank PERIPHERAL SETUP 7 8 TECHNICAL REFERENCE...
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