a single function and up to four interrupt lines for a multi-function device or
connector.
Interrupt A is used to request an interrupt. For a single function device, only
INTA# may be used, while the other three interrupt lines have no meaning.
Interrupt B, Interrupt C and Interrupt D are used to request additional interrupts
and only have meaning on a multi-function device.
IRDY#
Initiator Ready indicates the initiating agent’s (bus master’s) ability to complete
the current data phase of the transaction. IRDY# is used in conjunction with
TRDY#. During a write, IRDY# indicates that valid data is present on AD[31::0].
During a read, it indicates that the master is prepared to accept data.
LOCK#
Lock indicates an operation that may require multiple transactions to complete.
When LOCK# is asserted, non-exclusive transactions may proceed to an
address that is not currently locked.
PAR
Parity is even parity across AD[31::00] and C/BE[3::0]#. Parity generation is
required by all PCI agents. The master drives PAR for address and write data
phases; the target drives PAR for read data phases.
PAR64 (optional)
Parity Upper DWORD is the even parity bit that protects AD[63::32] and
C/BE[7::4]#. The master drives PAR64 for address and write data phases; the
target drives PAR64 for read data phases.
PERR#
Parity Error is for the reporting of data parity errors during all PCI transactions
except a Special Cycle. There are no special conditions when a data parity
error may be lost or when reporting of an error may be delayed.
PRSNT1# and PRSNT2#
PRSNT1# and PRSNT2# are related to the connector only, not to other PCI
components. They are used for two purposes: indicating that a board is
physically present in the slot and providing information about the total power
requirements of the board.
REQ#
Request indicates to the arbiter that this agent desires use of the bus. This is
a point to point signal. Every master has its own REQ#.
PCI REFERENCE
TECHNICAL REFERENCE
2-17
Summary of Contents for SB586TCP/166
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