otherwise, these bits are reserved but are stable and indeterminate. During a
data phase, an additional 32 bits of data are transferred when REQ64# and
ACK64# are both asserted.
C/BE[3::0]#
Bus Command and Byte Enables are multiplexed on the same PCI pins.
During the address phase of a transaction, these pins define the bus command;
during the data phase they are used as byte enables. The byte enables are
valid for the entire data phase and determine which byte lanes carry meaningful
data. C/BE0# applies to byte 0 (lsb) and C/BE3# applies to byte 3 (msb).
C/BE[7::4]# (optional)
Bus Command and Byte Enables are multiplexed on the same pins. During
an address phase (when using the DAC command and when REQ64# is
asserted), the actual bus command is transferred on C/BE[7::4]#; otherwise,
these bits are reserved and indeterminate. During a data phase, C/BE[7::4]#
are byte enables indicating which byte lanes carry meaningful data when
REQ64# and ACK64# are both asserted. C/BE4# applies to byte 4 and
C/BE7# applies to byte 7.
CLK
Clock provides timing for all transactions on PCI and is an input to every PCI
device.
DEVSEL#
Device Select, when actively driven, indicates that the driving device has
decoded its address as the target of the current access. As an input, DEVSEL#
indicates whether any device on the bus has been selected.
FRAME#
Cycle Frame is an interface control pin which is driven by the current master
to indicate the beginning and duration of an access. When FRAME# is
asserted, data transfers continue; when it is deasserted, the transaction is in
the final data phase.
GNT#
Grant indicates to the agent that access to the bus has been granted. This is
a point to point signal. Every master has its own GNT#.
IDSEL
Initialization Device Select is used as a chip select during configuration read
and write transactions.
INTA#, INTB#, INTC#, INTD# (optional)
Interrupts on PCI are optional and defined as "level sensitive," asserted low
(negative true), using open drain output drivers. PCI defines one interrupt for
PCI REFERENCE
2-16
TECHNICAL REFERENCE
Summary of Contents for SB586TCP/166
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