STATus Command
KIKUSUI Electronics Corp.
PWR-01 Interface Manual
Architecture
IEEE488.2 and SCPI registers are used for the status reports.
In each SCPI status register, there are the following sub registers: CONDition regis-
ter, EVENt register, ENABle register, PTRansition filter, and NTRansition filter.
-> Tutorial “Status Monitoring”
CONDition register
The transition of the CONDition register is automatic and reflects the condition of
the PWR-01 in real-time. Reading this register does not affect the contents.
EVENt register
The EVENt register bits are automatically set according to the changes in the CON-
Dition register. The rule varies depending on the positive and negative transition
filters (PTRansition and NTRansition). The EVENt register is reset when it is read.
ENABle register
The ENABle register enables the reports to the summary bit or status bit of the
event bit.
Transition filter
The PTRansition (positive transition) filter is used to report events when the condi-
tion changes from false to true.
The NTRansition (negative transition) filter is used to report events when the condi-
tion changes from true to false.
If both the positive filter and the negative filter are set to true, events can be report-
ed each time the status changes.
If both filters are cleared, event reporting is disabled.
Status byte register
The status byte register stores STB and RQS (MSS) messages as defined by the
IEEE488.1 standard. The status byte register can be read using IEEE488.1 serial
polling or the IEEE488.2 common command *STB?.
When serial polling is carried out, bit 6 responds with the request service (RQS).
The status byte value is not changed by serial polling.
*STB? makes the device transmit the contents of the status byte register and the
master status summary (MSS) message.
*STB? does not change the status byte, MSS, or RQS.
Bit Bit
weight
Bit name
Description
0
1
Reserved
Reserved for future use by the IEEE488. The bit value
is notified as zero.
1
2
Reserved
2
4
Error/Event Queue
If data exists in the error or event queue, this bit is set to
true.
3
8
Questionable Status
Register (QUES)
This bit is set to true when a bit is set in the QUEStion-
able event status register and the corresponding bit in
the QUEStionable status enable register is true.
4
16
Message Available
(MAV)
This bit is set to true when a request is received from
the digital programming interface and the PWR-01 is
ready to output the data byte.
5
32
Standard Event Status
Bit Summary (ESB)
This bit is set to true when a bit is set in the event status
register.
6
64
Request Service
(RQS)
This bit is set to true when a bit is set in the service
request enable register, and the corresponding bit exists
in the status byte.
The SRQ line of the GPIB is set.
Master Status Sum-
mary (MSS)
This bit is set to true when a bit in the status byte reg-
ister is set to 1 and the corresponding bit in the service
request enable register is set to 1.
7
128
Operation Status Reg-
ister (OPER)
This bit is set to true when a bit is set in the OPERation
event status register and the corresponding bit in the
OPERation status enable register is set.
8-15
Not Used
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