Hardware Description
6
NAND flash has a different organisation of transistors than the commonly used NOR flash.
While it allows a much higher density and thus an increase in storage capacity, there are
some differences which need to be kept in mind.
Typically, NAND flash is organized in pages and blocks, similar to hard disks. Pages are
512, 2048 or 4096 bytes in size, typical block sizes are 16, 128, 256 or 512 KB. Reading and
programming are performed on a page basis. Programming can only be done sequently
in one block.
Additionally, NAND flash requires bad block management, either by the driver software
or by a separate controller chip. Most NAND devices are shipped with bad blocks. These
are identified and marked according to a specified bad block strategy. Further bad blocks
may be detected during runtime. They are detected via an ECC (error correcting code). If
a bad block is detected, the data is written to a different, good block, and the bad block
table is updated. So the overall memory capacity gradually shrinks as more and more
blocks are marked bad.
This error detection is done by software like U-boot and Linux. Additionally, NAND flash is
subject to a limited number of write and erase cycles. These are typically 100.000 cycles
per block. So it is highly recomended to use wear levelling filesystems.
4.3.2. LPDDR-SDRAM
The Stamp9G45 is equipped with 128MB LPDDR-SDRAM (Low power DDR-SDRAM).
Customer specific adaptations allow configurations up to 512MB. In 128MB and 256MB
configurations, the LPDDR-SDRAM is connected to EBI0. The external Bus is not affected.
In 512MB configuration 256MB of the LPDDR-SDRAM are connected to chip select one
(NCS1) of the micrcontroller's EBI1.
DDR-SDRAM allows random access to any of its memory area and is volatile memory.
DDR-SDRAM (Double Data Rate) takes over data at the rising and falling edge of a clock
pulse, thus achieving almost twice the bandwidth than a similar connected SDRAM. It has
a synchronous interface, that means it waits for a clock signal before responding to control
inputs and is therefore synchronized with the CPU bus. The clock is used to drive a final
state machine in the chip, which allows to accept new instructions, before the previous
one has finished executing.
4.3.3. EEPROM
The Stamp9G45 is equipped with a 128 bytes EEPROM, connected to the Dallas
™
1 wire
bus.
EEPROM stands for Electrically Erasable Programmable Read-Only Memory and is
non-volatile memory, which is used to store small amounts of data like calibration or
configuration data. EEPROMS are byte-wise erasable, thus allowing true random access.
4.3.4. SRAM
The Stamp9G45's microcontroller is equipped with 64 KB internal SRAM. The internal
SRAM can be accessed in one bus cycle and may be used for time critical sections of code
or interrupt handlers.
