Counter/Timers (8254)
D7
D6
D5
D4
D3
D2
D1
D0
SC1
SC0
0
0
X
X
X
X
I/O Address = 43h
RD = 1
WR = 0
SC1, SC0 - specify counter to be latched
SC1
SC0
Counter
0
0
1
1
0
1
0
1
0
1
2
Read-Back Command
D5, D4 - 00 designates Counter Latch Command
X - don't care
Note: Don't care bits (X) should be 0 to ensure future compatibility
Figure 11–4. Counter Latch Command Format.
The selected counter’s output latch (OL) latches the count at the time
the Counter Latch command is received. This count is held in the
latch until it is read by the CPU or until the counter is reprogrammed.
The count is then unlatched automatically and the OL returns to
"following" the counting element (CE). This allows reading the
contents of the counters dynamically without affecting counting in
progress. Multiple Counter Latch commands may be used to latch
more than one counter. Each latched OL holds the count until read.
11-9
