Interrupt Controller (8259A)
Interrupt Request Register (IRR)
All interrupt requests are input to the Interrupt Request register (IRR).
The 8-bit IRR maintains a bit position for each interrupt input. A
requesting interrupt sets the bit position to logical 1. The bit is
automatically reset during the interrupt acknowledge cycle. The
application program can read the IRR to determine the status of the
requesting interrupts.
The PIC has eight interrupt inputs, IR0 through IR7. Figure 12-5 on
page 12-23 illustrates the interrupt options available on the
ZT 8809A. Each interrupt source is available at a wirewrap pin, and
one of each pair of wirewrap pins is jumper selected to drive the
interrupt at the PIC. Refer to Appendix A to reassign these jumpers.
Pay particular attention to those jumper selections required by STD
DOS.
Interrupt Mask Register (IMR)
All interrupt requests are seen by the Interrupt Request register. The
Interrupt Mask register (IMR) is used as a filter to these interrupt
requests, selectively disabling them from being serviced. The IMR is
an 8-bit register with one bit for each interrupt input. Setting a bit to
logical 1 prevents the respective interrupt request from being trans-
ferred from the Interrupt Request register to the interrupt In-Service
register (ISR).
12-8
