Interrupt Controller (8259A)
OPERATION OF THE INTERRUPT CONTROLLER
Interrupt operation of the 8259A falls under three categories:
priorities, triggering, and status. Each category uses various modes
and commands, as discussed below. Additional information can be
found in Intel’s 8259A data sheet and application note AP-59.
Priorities
The 8259A can be programmed to operate in one of the following
modes:
•
Fully Nested Mode
•
Special Fully Nested Mode
•
Automatic Rotating Mode
•
Specific Rotating Mode
•
Special Mask Mode
•
Poll Mode
Fully Nested Mode
In this mode, PIC input signals are assigned a priority from 0 through
7. Interrupt IR0 has the highest priority and IR7 has the lowest
priority.
This is the normal operation mode of the PIC unless
specifically programmed otherwise.
When an interrupt is acknowledged, the highest priority request is
available to the CPU. Lower priority interrupts are inhibited; higher
priority interrupts are able to generate an interrupt that will be
acknowledged if the 8088 has enabled its own interrupt. The End-Of-
Interrupt (EOI) command from the CPU is required to reset the PIC
for the next interrupt.
12-24
