INDUSTRIAL I/O PACK SERIES APCe8650
PCI BUS CARRIER BOARD
Acromag, Inc. Tel: 248-295-0310
- 17 -
www.acromag.com
Carrier Status/Control Register - (Read/Write, P 00H)
The Carrier Board Status Register reflects and controls functions globally on
the carrier board. This includes monitoring the IP Error signal, enabling,
disabling, or monitoring IP and timeout interrupts and performing a software
reset.
Table 3-4 Carrier Status / Control Register Bit Assignment
BIT
FUNCTION
15-9
Not Used (bits read as logic “0”)
8
Write
Only
Software Reset
Writing a “1” to this bit causes a software reset. Writing a “0” or
reading this bit has no effect. When set, the software reset
pulse will have duration of 1 microsecond.
7
Not Used (bit reads as logic “0”)
6
Read
Only
FLASH Busy
This bit will be “1” when a read or write to the ID FLASH is in
progress. On initial application of power, a FLASH read
sequence is automatically initiated to retrieve the ID bytes from
the FLASH. The read sequence will take less than 5
microseconds. The ID bytes are stored in the ID register.
Reading the ID register does not trigger a FLASH read sequence.
A write to the ID register will initiate a FLASH write / read
sequence that could take up to 3 seconds to complete. The
busy bit will be “1” while the write / read sequence is in
progress.
5
Read
And
Write
IP Module Access Time Out Interrupt Pending
This bit will be "1" when there is an IP Module Access Time Out
interrupt pending. This bit will be "0" when there is no interrupt
pending. Reset condition: Set to "0". Writing a “1” to this bit
will release the pending interrupt.
4
Read
Only
IP Module Access Time Out Status
Indicates the last IP module access has timed out. This bit only
reflects the last IP module access.
“0” if last IP module access did not time out.
“1” if last IP module access did time out.
3
Read
And
Write
Time Out Interrupt Enable
When set to “1”, this bit will enable the carrier board to
generate an interrupt upon time out of an IP module access.
The default setting or reset condition is “0” (interrupt
generation upon time out disabled). The interrupt service
routine must set this bit to 0 to clear the pending interrupt
request.
2
Read
And
Write
IP Module Interrupt Enable
When set to “1”, this bit will enable the generation of IP module
interrupts. The reset condition is “0”, (IP module interrupt
generation disabled). Interrupts must also be supported and
configured in the IP modules.
