INDUSTRIAL I/O PACK SERIES APCe8650
PCI BUS CARRIER BOARD
Acromag, Inc. Tel: 248-295-0310
- 23 -
www.acromag.com
Carrier Board Clock Circuitry
An 80 MHz oscillator is used to clock the FPGA. The 32 MHz or 8 MHz IP bus
clocks are generated from the 80 MHz clock by a phased locked loop internal
to the FPGA. Clocks are then driven to each IP module via a high speed
transceiver to allow for a module independent selectable clock. All clock lines
include series damping resistors to reduce clock overshoot and undershoot.
PCI Interrupter
Interrupts are initiated from an interrupting IP module. However, the carrier
board will only pass an interrupt generated by an IP module to the PCI bus if
the carrier board has been first enabled for interrupts. Each IP module can
initiate two interrupts which can be individually monitored on the carrier
board. After interrupts are enabled on the carrier board via the Interrupt
Enable Bits (see section 3 for programming details), an IP generated interrupt
is recognized by the carrier board and is recorded in the carrier board’s
Interrupt Pending Register.
A carrier board pending interrupt will cause the board to pass the interrupt to
the PCIe bus provided the Interrupt Enable bits of the carrier’s Status Register
have been enabled (see section 3 for programming details). The PC interrupt
request line assigned by the system configuration software will then be
asserted. The PC will respond to the asserted interrupt line by executing the
interrupt service routine corresponding to the interrupt line asserted. The
interrupt service routine is executed only if the IRQ on the PC’s interrupt
controller has been previously unmasked (see section 3 for programming
details).
The interrupt service routine should respond to an interrupt by accessing IP
Interrupt Select (INTSEL*) space. The interrupt service routine should also
conclude the interrupt routine by writing the “End-Of-Interrupt” command to
the PC’s 8259 interrupt controller (see section 3 for more details).
Power Failure Monitor
The carrier board contains a 5 volt under voltage monitoring circuit which
provides a reset to the IP modules when the 5 volt power drops below 4.5
volts typical / 4.37 volts minimum. This circuitry is implemented per the
Industrial I/O Pack specification.
Power-On Reset
The carrier board will provide an asynchronous reset signal to all IP modules
for at least 100ms following power-up. The IP reset signal will remain active
until the FPGA is initialized.
Power Supply Fuses
The +5V supply lines to each of the IP modules are individually fused with a
current limit of 2 amps minimum. In addition, the +12 V, and -12 V supply
lines to each of the IP modules are individually fused with a current limit of 1
