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Instruction Set Extension Fabric (ISEF)
The Stretch Extension Unit is the key to its DSP-like performance. It is tightly integrated within
the chip and consists of the following:
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The Wide Register File – a set of 128-bit wide registers for holding data (three ports for
read and one port for write from inside the ISEF fabric)
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The Special Registers – a collection of support registers for a variety of functions
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Two Instruction Set Extension Fabric (ISEF) units – an FPGA-like configurable set of bit-
slice computational resources that implement Stretch Extension Instructions.
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The SCP 128-bit internal bus can load and store a wide register each cycle, if data is
available from the Data cache or blocks of internal data SRAM, a little bit longer if data is
stored in the external SDRAM.
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Each ISEF fabric can be configured to support eight Extended Instructions for a total of 16
per ISEF unit.
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An Extension Instruction can be issued every third cycle in the S5610 to be executed
concurrently with other Extended Instructions in progress.
An Extended Instruction can be quite complex and will take multiple cycles to complete
instruction depending on its code. Once issued, an Extended Instruction continues its
computations concurrently with the base Xtensa ISA processing. The S5610 allows up to 31
clock cycles per Extended Instruction. The number of Extended Instructions in an application is
not limited to a single ISEF set since one ISEF fabric can be re-loaded with new Extended
Instructions while the other goes on processing.
Results of an Extended Instruction can be stored in the Wide Register File to be used by the
following ISEF instructions or stored in one of the SCP memories. The need to feed data to the
ISEF unit and fetch results of processing via the SCP 128-bit interconnect is often the real
determinant of the ISEF computational performance. Extensive use of the Wide Register File
and internal memories for intermediate results can help but will not eliminate the necessity of
maintaining the data flow through the SCP at the rate specified by an application and the
external video data sources.
User programs the ISEF unit in C programming language by identifying kernels of data-
intensive iterative computations and designating kernels to be placed in the ISEF and replaced
by an Extension Instruction in the Xtensa code flow. There is a trade-off between amount of
ISEF resources used by an Extended Instruction and a number of such instructions directly
addressable without reloading. An application must explicitly load ISEF instructions to make
use of them.
To maximize execution speed of an Extended Instruction, the programmer can analyze its
interlocks with the Pipeline Analyzer tool and make changes in the instruction flow to avoid
resource contention. The resource savings can be significant and more than double the speed
of execution. Ultimately, the ISEF computational resources are finite and the user-defined
Extended Instruction can run out of the available bit-slices necessitating instruction re-design or
even splitting in two.
