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controlled by the SCP via the Stretch-accessible registers in the FPGA. The SysAD bus
features include:
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1+ GB/sec bandwidth – 64-bits at 200 MHz
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Multiplexed address-data bus
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36-bits pf physical address
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64-bits of data
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Support for two outstanding read requests, which can be returned out of order
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Simple state machine that uses minimal amount of resources in the FPGA
GigE MACs
The Stretch Gigabit Ethernet MACs connect directly to the chip data interconnect and
communicate with an external Quad-PHY chip via the standard Gigabit Media Independent
Interface (GMII). Each GMAC has the built-in Transmit and Receive FIFO and two dedicated
channels in the SCP DMA controller that moves data in and out of FIFOs.
S5610 Low and Mid-speed Peripherals
Stretch S5610 has a variety of built-in low and mid-speed peripheral devices that simplify
construction of a rich embedded system around this chip and enhance its functionality.
The mid-speed peripheral interfaces include one Generic Interface Bus (GIB) that is used on
Fast-X board to control setting on programmable parts and two Streaming Serial Ports (SSPort)
that are not used.
Among the low-speed interfaces are two Universal Asynchronous Receiver/Transmitter ports
that control settings of the CameraLink devices.
Interrupt Controller
For detailed information about the Stretch S5610 SCP, the user is referred to the SCP
Architectural Reference, parts 1, 2 and 3 and to the S5000 Peripheral Reference. A full set of
Stretch documentation is available with the Stretch IDE toolset.
All on-board interrupts from the Fast-X various devices are forwarded to the Stretch processor
and will be handled locally. This configuration allows much faster interrupt processing under the
SCP real-time OS environment and protects HOST OS from an excessive amount of interrupts
it is not well equipped to handle.
PCI-X
I
NTERFACE TO
H
OST
C
OMPUTER
The Fast-X interface to the PCI-X Host bus is provided by the Stretch SCP internal PCI-X
controller.
The Stretch PCI-X supports the following features
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Compliance with PCI-X Bus Specification Rev. 2.3
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Compliance with PCI-X Addendum Revision 1.0a
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64-bit PCI-X interface
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Synchronous 0–133 MHz PCI-X-to-application clock frequencies
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Support for up to 2 Master Deferred Read transactions
