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15 

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Support for up to 8 Target Delayed Read transactions 

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Support for up to 16 Target Split Read-Write transactions 

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Support for up to 2 Master Split Read-Write transactions 

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Programmable PCI Target Burst Read disconnect (from 16 KBytes to 64 KBytes, aligned)

 

 

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PCI Target Burst size of up to 2 MBytes, aligned 

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PCI and PCI-X Master Burst size of up to 256 KBytes (2 MBytes, aligned) 

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PCI-X Target Burst size of up to 256 KBytes (2 MBytes, aligned) 

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PCI-X interface connector is keyed to  3.3V signaling 

F

AST

-X

 

POWER-UP

 

SEQUENCE 

The Fast-X software-controlled procedure for power-up and module initialization follows 

this sequence: 

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3.3V Power Applied 

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2.5/1.8V power stabilizes.  The time this takes depends on the 3.3V ramp-rate. 

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CPLD configures from the attached serial FLASH. 

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STRETCH S5610 boots from the FLASH memory 

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Host processor performs BIOS scan and configures STRETCH S5610 PCI-X 
resources. 

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Host processor loads STRETCH program into STRETCH SDRAM, and starts 
STRETCH application. 

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STRETCH initialization code configures Front-End FPGA. 

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Software initializes on-board registers via Stretch GPIO controller. 

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Data capture may begin. 

 

SOFTWARE OVERVIEW 

The Fast-X is delivered fully functional, bundled with the video capture program, 

Fast Motion

 

that supports video preview and permits saving captured video stream on disk. 

Fast Motion 

includes an assortment of the camera definition files for the most popular models. Fast Motion 
allows the user to modify many video capture parameters: frame rate, frame exposure, frame 
size, position of Region-Of-Interest in a frame, and others.  The user can designate which 
directory or folder to store captured video.   

The Fast-X significant on-board computational resources qualify it as an embedded computing 
system with DSP and ISP capabilities. It offers to the machine vision application developer or 
OEM a whole new dimension in customization. There are two software components that can be 
modified by the user: Host-resident and Board-resident software. The two software components 
communicate and synchronize their activity via the services provided by the Alacron Real-Time 
operating system (

ALRT

) residing on the Fast-X board with the 

ALRT

 driver running on the 

HOST computer. A Fast-X application developer writes both software components in the C/C++ 
development environments for the HOST processor and for the Stretch SCP using 
corresponding components of the 

ALRT 

Board-Support Package. 

Summary of Contents for FAST-X

Page 1: ...1 FAST X TECHNICAL PRODUCT DESCRIPTION 30002 00192...

Page 2: ...chnical Product Description Document Number 30002 00192 Revision History 1 0 October 25 2006 Trademarks Alacron is a registered trademark of Alacron Inc Channel Link is a trademark of National Semicon...

Page 3: ...ic ISEF 12 Memory System 13 SysAD Interface 13 GigE MACs 14 S5610 Low and Mid speed Peripherals 14 Interrupt Controller 14 PCI X Interface to Host Computer 14 Fast X POWER UP SEQUENCE 15 SOFTWARE OVER...

Page 4: ...f they did not come in your FastSeries shipment 30002 00148 ALFAST Runtime Software Programmer s Guide Reference 30002 00150 FastSeries Library User s Manual 30002 00169 ALRT Runtime Software Programm...

Page 5: ...dth from faster higher resolution or from multiple simultaneous sources of video data The on board video processing will prevent the Host computer system from experiencing unpredictable stalls and fro...

Page 6: ...sed with 3 Basic Camera Link cameras 1 Basic and 1 Medium Camera Link cameras 1 Full Camera Link camera 1 Trans standard Camera Link camera with 10 taps by 8bit Four 4 Gigabit Ethernet RJ 45 ports wil...

Page 7: ...erations made possible by local application boot of the Stretch S5610 processor from 32MB of on board FLASH HARDWARE OVERVIEW This chapter provides an overview of Fast X hardware functional units and...

Page 8: ...s It also provides image processing capabilities using two FPGA like programmable fabrics extending its traditional processor architecture The sizeable up to 2GB and fast Stretch SDRAM memory has suff...

Page 9: ...s up to three 3 Camera Link interfaces each of which can run at up to 85 MHz J1 J2 J3 1 CL Base CL Base CL Base 2 CL Medium CL Base 3 CL Full N A Table 1 Fast x Camera Link Configurations Alacron can...

Page 10: ...the headers attached to each video frame Front end processing can include compiling histogram finding maxima and minima and pixel wise table transformations Depending on the video bandwidth the Front...

Page 11: ...itude boost in the data processing speed just where it is necessary Similarly to FPGA the ISEF units are most effective when processing fixed point data Floating point data processing should be done u...

Page 12: ...EF fabric can be re loaded with new Extended Instructions while the other goes on processing Results of an Extended Instruction can be stored in the Wide Register File to be used by the following ISEF...

Page 13: ...nal devices It includes 256KB on chip single port SRAM 32KB dual port data SRAM 32KB Data cache 32KB Instruction cache DDR SDRAM controller to up to 3GB of external SDRAM The SCP DDR SDRAM controller...

Page 14: ...control setting on programmable parts and two Streaming Serial Ports SSPort that are not used Among the low speed interfaces are two Universal Asynchronous Receiver Transmitter ports that control sett...

Page 15: ...may begin SOFTWARE OVERVIEW The Fast X is delivered fully functional bundled with the video capture program Fast Motion that supports video preview and permits saving captured video stream on disk Fa...

Page 16: ...soft Windows XP operating systems Alacron offers Board Support Packages for Microsoft Windows and Linux OS environments Figure 6 Fast X Software Development Environment HOST SYSTEM REQUIREMENTS In ord...

Page 17: ...f dll STRETCH SOFTWARE DEVELOPMENT Software development for the Fast X on board applications targets the Stretch SCP and uses the Stretch Interactive Development Environment Stretch IDE toolkit The St...

Page 18: ...gure 7 Fast X Stretch IDE The picture in the upper left panel of the Figure 7 shows a detailed view of the SCP instruction pipeline including concurrent execution of Extended Instructions in the ISEF...

Page 19: ...19 The typical development flow for the SCP looks like the diagram below c Figure 8 Fast X Stretch software development flow...

Page 20: ...XIN0 25 13 ground ground 26 Table 2 Pinout of J1 and J3 CameraLink Connectors J2 Full Medium Pos Base Config Configuration Base Config Pos 1 shield shield shield shield 14 2 CC4 Z3 Z3 CC4 15 3 CC3 ZCL...

Page 21: ...ck are controlled directly by the GMAC and by the software that runs it APPENDIX C HEADERS AND JUMPERS Header Description P1 GigE QuadPHY JTAG P2 Write Protect jumpers for CPLD and Stretch FLASH Memor...

Page 22: ...e problem you are experiencing The release notes are available in the directory usr alacron alinfo _____ Compile and run the example programs found in the directory usr alacron src examples _____ Find...

Page 23: ...rs and hardware revision numbers of all of your boards This information is written on the invoice that was shipped with your products _____ Also each board has its serial number and revision number wr...

Page 24: ...shipped back _____ A listing including revision numbers for all software libraries applications daughter cards etc _____ A clear and detailed description of the problem and when it occurs _____ Exact...

Page 25: ...ternet access or if it is inconvenient for you to get to access copy the code to a disk describe the error and mail the disk to Technical Support at the Alacron address below If the code is small enou...

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