224
4317I–AVR–01/08
AT90PWM2/3/2B/3B
19.6.4
EUSART Control Register B – EUCSRB
• Bit 7:5 –Reserved Bits
These bits are reserved for future use. For compatibilty with future devices, these bits must be
written to zero when EUSCRB is written.
• Bit 4 – EUSART Enable Bit
Set to enable the EUSART mode, clear to operate as standard USART.
• Bit 3– EUSBS Enable Bit
This bit selects the number of stop bits detected by the receiver.
Note:
The number of stop bit inserted by the Transmitter in EUSART mode is configurable throught the
USBS bit of in the of the USART.
• Bit 2–Reserved Bit
This bit is reserved for future use. For compatibilty with future devices, this bit must be written to
zero when EUSCRB is written.
• Bit 1 – Manchester mode
1
0
0
1
14-bit
1
0
1
0
15-bit
1
0
1
1
16-bit
1
1
0
0
Reserved
1
1
0
1
Reserved
1
1
1
0
16 OR 17 bit (for Manchester
encoded only mode)
1
1
1
1
17-bit
Table 19-2.
URxS Bits Settings
URxS3
URxS2
URxS1
URxS0
Receive Character Size
Bit
7
6
5
4
3
2
1
0
-
-
-
EUSART
EUSBS
-
EMCH
BODR
EUCSRB
Read/Write
R
R
R
R/W
R/W
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Table 19-3.
EUSBS Bit Settings
EUSBS
Receiver Stop Bit(s)
0
1-bit
1
2-bit
