Principles of Operation
6-6
6.4.2 Switching card logic
See Figure 6-6 for a block diagram of the logic on a typical
switching card.
On the cards, the CLK and RELAYDATA signals are buff-
ered and sent to a string of UCN-5841 serial input latched
driver chips. The CLK signal is sent in parallel to all of the
driver ICs. The serial data out of one driver is connected to
the serial data in of the next driver.
ID data circuits
Each card has a 2764 EPROM that contains the following
identification data:
• Card model number
• Relay (hardware) settling time
• Relay configuration table
The configuration table defines the location of each relay
driver within the serial RELAYDATA bit stream. The table is
necessary because the physical layout of cards varies. In
addition, the table accommodates row and/or column isola-
tion relays, such as those on the Model 7072 card.
To read this ID data, the following sequence is performed at
power-up. Figure 6-7 shows the general timing of this
sequence.
Figure 6-5
Matrix card interface timing diagram
E
SELECT RELAYDATA
ACTIVE
U130 OUTPUT Q
CLK
RELAYDATA
U25 CLK
8th Rising Edge
etc.
D7
D6
D5
D4
D3
D2
D1
D0
1. The CARDSEL line is brought low, enabling the
EPROM outputs. This line remains low throughout the
ID data transmission sequence.
2. The CLRADDR line (generated by port signal PB3 of
the digital boards VIA) is pulsed high to clear the 12-bit
address counter (74HCT4040) to zero. At this point, an
EPROM address of zero is selected. This pulse occurs
only once.
3. The NEXTADDR line (PB2 of VIA) is set low. This
increments the counter and enables parallel loading of
the parallel-to-serial converter (74HCT165). NEXT-
ADDR is kept low long enough for the counter to
increment and the EPROM outputs to stabilize. This
sequence functions because the LOAD input of the
parallel-to-serial converter is level-sensitive rather than
edge-sensitive. The first EPROM address used by the
Model 708A is location one, not zero.
4. The same CLK signal that shifts RELAYDATA into the
relay driver also clocks the parallel-to-serial converter to
shift all eight data bits from the converter to the digital
board via the IDDATA line. This means that a byte of
RELAYDATA must be sent to a card to get the next byte
of IDDATA.
Steps 3 and 4 are repeated until all the necessary EPROM
locations are read.
As shown in Figure 6-7 of the mother board, IDDATA is con-
verted back to parallel by U102 (74HCT164) and is read by
the microprocessor through the port A lines of U103 (6522A
VIA)(VIA $3860-$386F).
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