Table 8: Completer Completion Interface Port Descriptions (cont'd)
Port
I/O
Width
Description
pcie0_s_axis_cc_tready
pcie1_s_axis_cc_tready
O
4
Completer Completion Data Ready.
Activation of this signal by the core indicates that it is
ready to accept data. Data is transferred across the
interface when both pcie(n)_s_axis_cc_tvalid and
pcie(n)_s_axis_cc_tready are asserted in the same cycle.
If the core deasserts the ready signal when the valid
signal is High, the user application must maintain the
data on the bus and keep the valid signal asserted until
the core has asserted the ready signal.
Table 9: Sideband Signal Descriptions in pcie(n)_s_axis_cc_tuser
Bit Index
Name
Width
Description
0
discontinue
1
This signal can be asserted by the user application during a
transfer if it has detected an error (such as an uncorrectable
ECC error while reading the payload from memory) in the
data being transferred and needs to abort the packet. The
core nullifies the corresponding TLP on the link to avoid
data corruption.
The user application can assert this signal during any cycle
during the transfer. It can either choose to terminate the
packet prematurely in the cycle where the error was
signaled, or can continue until all bytes of the payload are
delivered to the core. In the latter case, the core treats the
error as sticky for the following beats of the packet, even if
the user application deasserts the discontinue signal before
the end of the packet.
The discontinue signal can be asserted only when
pcie(n)_s_axis_cc_tvalid is High. The core samples this signal
only when pcie(n)_s_axis_cc_tready is High. Thus, when
asserted, it should not be deasserted until
pcie(n)_s_axis_cc_tready is High.
When the core is configured as an Endpoint, this error is
also reported by the core to the Root Complex to which it is
attached, using AER.
32:1
parity
32
Odd parity for the 256-bit data.
When parity checking is enabled in the core, user logic must
set bit i of this bus to the odd parity computed for byte i of
pcie(n)_s_axis_cc_tdata. Only the lower 16 bits are used
when the interface width is 128 bits, and only the lower 8
bits are used when the interface width is 64 bits.
When an interface parity error is detected, it is recorded as
an uncorrectable internal error and the packet is discarded.
According to the Base Spec 6.2.9, an uncorrectable internal
error is an error that occurs within a component that results
in improper operation of the component. The only method
of recovering from an uncorrectable internal error is a reset
or hardware replacement.
The parity bits can be permanently tied to 0 if parity check is
not enabled in the core.
Chapter 3: Product Specification
PG346 (v3.3) November 16, 2022
CPM Mode for PCI Express
46
