Table 11: Sideband Signal Descriptions in pcie(n)_s_axis_rq_tuser
Bit Index
Name
Width
Description
3:0
first_be[3:0]
4
Byte enables for the first Dword.
This field must be set based on the desired value of the
First_BE bits in the Transaction-Layer header of the request
TLP. For Memory Reads,
I/O Reads, and Configuration Reads, these four bits indicate
the valid bytes to be read in the first Dword. For Memory
Writes, I/O Writes, and Configuration Writes, these bits
indicate the valid bytes in the first Dword of the payload.
The core samples this field in the first beat of a packet,
when pcie(n)_s_axis_rq_tvalid and pcie(n)_s_axis_rq_tready
are both High.
7:4
last_be[3:0]
4
Byte enables for the last Dword.
This field must be set based on the desired value of the
Last_BE bits in the Transaction-Layer header of the TLP. For
Memory Reads of two Dwords or more, these four bits
indicate the valid bytes to be read in the last Dword of the
block of data. For Memory Reads and Writes of one DW
transfers and zero length transfers, these bits should be 0s.
For Memory Writes of two Dwords or more, these bits
indicate the valid bytes in the last Dword of the payload.
The core samples this field in the first beat of a packet,
when pcie(n)_s_axis_rq_tvalid and pcie(n)_s_axis_rq_tready
are both High.
10:8
addr_offset[2:0]
3
When the address-aligned mode is in use on this interface,
the user application must provide the byte lane number
where the payload data begins on the data bus, modulo 4,
on this sideband bus. This enables the core to determine
the alignment of the data block being transferred.
The core samples this field in the first beat of a packet,
when pcie(n)_s_axis_rq_tvalid and pcie(n)_s_axis_rq_tready
are both High.
When the requester request interface is configured in the
Dword-alignment mode, this field must always be set to 0.
In Root Port configuration, Configuration Packets must
always be aligned to DW0, and therefore for this type of
packets, this field must be set to 0 in both alignment modes.
11
Discontinue
1
This signal can be asserted by the user application during a
transfer if it has detected an error in the data being
transferred and needs to abort the packet. The core nullifies
the corresponding TLP on the link to avoid data corruption.
You can assert this signal in any cycle during the transfer.
You can either choose to terminate the packet prematurely
in the cycle where the error was signaled, or continue until
all bytes of the payload are delivered to the core. In the
latter case, the core treats the error as sticky for the
following beats of the packet, even if the user application
deasserts the discontinue signal before the end of the
packet.
The discontinue signal can be asserted only when
pcie(n)_s_axis_rq_tvalid is High. The core samples this signal
only when pcie(n)_s_axis_rq_tready is High. Thus, when
asserted, it should not be deasserted until
pcie(n)_s_axis_rq_tready is High. Discontinue is not
supported for Non-Posted TLPs. The user logic can assert
this signal in any cycle except the first cycle during the
transfer.
When the core is configured as an Endpoint, this error is
also reported by the core to the Root Complex to which it is
attached, using Advanced Error Reporting (AER).
Chapter 3: Product Specification
PG346 (v3.3) November 16, 2022
CPM Mode for PCI Express
49
