Table 25: Sideband Signals in pcie(n)_s_axis_cc_tuser (cont'd)
Bit Index
Name
Width
Description
36
discontinue
1
This signal can be asserted by the user application during a
transfer if it has detected an error (such as an uncorrectable
ECC error while reading the payload from memory) in the
data being transferred and needs to abort the packet. The
core nullifies the corresponding TLP on the link to avoid
data corruption.
The user logic can assert this signal in any beat during the
transfer except the first beat of the TLP. It can either choose
to terminate the packet prematurely in the cycle where the
error was signaled, or continue until all bytes of the payload
are delivered to the core. In the latter case, the core treats
the error as sticky for the following beats of the packet, even
if the user logic deasserts the discontinue signal before the
end of the packet.
The discontinue signal can be asserted only when
pcie(n)_s_axis_cc_tvalid is High. The core samples this signal
only when pcie(n)_s_axis_cc_tready is High. Thus, once
asserted, it should not be deasserted until
pcie(n)_s_axis_cc_tready is High.
When the straddle option is enabled on the CC interface, the
user should not start a new TLP in the same beat when a
TLP is ending with discontinue asserted.
When the core is configured as an Endpoint, this error is
also reported by the core to the Root Complex it is attached
to, using Advanced Error Reporting (AER).
164:137
parity
128
Odd parity for the data. When parity checking is enabled in
the core, user logic must set bit i of this bus to the odd
parity computed for byte i of pcie(n)_s_axis_cc_tdata.
On detection of a parity error, the core nullifies the
corresponding TLP on the link and reports it as an
Uncorrectable Internal Error.
The parity bits can be permanently tied to 0 if parity check is
not enabled in the core.
Requester Request Interface
Table 26: Requester Request Interface Port Descriptions (1024-bit Interface)
Name
Width
I/O
Description
pcie0_s_axis_rq_tdata
pcie1_s_axis_rq_tdata
1024
I
Requester-side request data from the user application to
the PCIe core.
pcie0_s_axis_rq_tuser
pcie1_s_axis_rq_tuser
449
I
This is a set of signals containing sideband information for
the TLP being transferred. These signals are valid when
pcie(n)_s_axis_rq_tvalid is high. The individual signals in this
set are described in the following table.
pcie0_s_axis_rq_tlast
pcie1_s_axis_rq_tlast
1
I
The user application must assert this signal in the last cycle
of a TLP to indicate the end of the packet. When the TLP is
transferred in a single beat, the user logic must set this bit
in the first cycle of the transfer.
This input is used by the core only when the straddle option
is disabled. When the straddle option is enabled, the core
ignores the setting of this input, using instead the is_sop/
is_eop signals in the s_axis_rq_tuser bus to determine the
start and end of TLPs.
Chapter 3: Product Specification
PG346 (v3.3) November 16, 2022
CPM Mode for PCI Express
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