Embedded Solutions
Page 10 of 37
If the TX clear is enabled, the transmitter will be automatically disabled and the TX
interrupt will be asserted when no more message frames have been requested. If the
TX clear is not enabled, the transmitter will remain enabled after the last message, but
the TX interrupt will still be asserted. When multiple frames are being sent, the frame
done interrupt will be asserted at the end of each message-frame. The TX interrupt will
only occur after the last frame and the transmitter will wait, pointing at the next address
after the end address. If additional data has been or is later written to the DPR, a new
message can be started by entering a new end address (and optionally a new start
address). The transmit state-machine will then start the new message and continue
sending data until the new end address has been reached. If the end address of the
message is less than the start address of the message, when the end of the DPR is
reached the transmitter will proceed to the beginning of the DPR and continue until the
end address is reached.
To receive a message the receiver must be enabled, but only the starting address of
the receive buffer is specified. Data will be stored sequentially in the next address after
that starting address and so on until the closing flag is detected. This will latch a
receiver done interrupt status and can cause an interrupt if enabled. The last address
that data was stored in is written to the starting address location for that message-
frame. This allows any received message to be quickly accessed in the received data
by reading the address pointer in the message start location, which points to the end
address of the first message-frame. The memory location following the end of the first
message-frame contains the end address of the second message-frame. This process
can be repeated as many times as needed to find the message of interest. At the end
of each frame, the end address is also latched and can be read from the control
register as a read-only field, but this will be overwritten as subsequent frames complete.
The transmit interrupt is mapped to the first interrupt line of the selected channel, the
transmit frame done interrupt is mapped to the second interrupt line, the receive
interrupt is mapped to the third interrupt line and the abort received interrupt is mapped
to the fourth interrupt line of the selected channel.
When a frame completes and no more message-frames are pending, the bus can stay
active by continually sending flags or it can go idle by sending ones. The SDLC Idle
After Frame Done control bit determines this behavior for the transmitter. If this bit is
not set and the bus remains active by sending multiple flags, the Repeated Flags Share
Zero control bit
determines whether the transmitter sends a ‘0111111001111110’ or a
‘011111101111110’ pattern while waiting for a new message-frame to be requested.
When the transmitter is disabled the bus defaults to a high state, which is equivalent to
the idle condition.
