200
Cycle Time
Section 8-3
Maximum I/O Response
Time
The Customizable Counter Unit takes longest to respond when it receives the
input signal just after the input refresh phase of the cycle, as shown in the
illustration below. In that case, a delay of approximately one cycle will occur.
When Cyclic Output Refreshing Is Used:
Maximum I/O response time = 0.05 + 0.202 + 0.1 = 0.352 ms
8-3-4
Interrupt Processing Time
This section explains the processing times involved from the time an interrupt
is executed until the interrupt processing routine is called, and from the time
an interrupt processing routine is completed until returning to the original posi-
tion. The explanation applies to the following four types of interrupts: Input
interrupts, interval timer interrupts, high-speed counter interrupts, and pulse
output interrupts. Refer to relative sections in
SECTION 7 Special Functions
for details on operation.
Processing Time
The table below shows the times involved from the generation of an interrupt
signal until the interrupt processing routine is called, and from when the inter-
rupt processing routine is completed until returning to the original position.
Generation and Clearing of Non-fatal Errors:
When a non-fatal error is generated and the error contents are registered at
the Customizable Counter Unit, or when an error is being cleared, interrupts
will be masked for a maximum of 55
m
s until the processing has been com-
pleted.
I/O refresh
Overseeing, etc.
Input ON delay
Input
point
Input
bit
Internal
processing
Instruction execution
Instruction execution
Output ON
delay
Output point
With cyclic output refresh
Instruction execution
Cycle time
Item
Contents
Time
Interrupt input ON delay
This is the delay time from the time the interrupt input bit turns ON
until the time that the interrupt is executed. This is unrelated to
other interrupts.
50
m
s
¯
(Interrupt condition realized.)
Standby until completion
of interrupt-mask pro-
cessing
This is the time during which interrupts are waiting until processing
has been completed. This situation occurs when a mask process is
executed. It is explained below in more detail.
See below.
¯
Change-to-interrupt pro-
cessing
This is the time it takes to change processing to an interrupt.
¯
(Interrupt processing routine executed)
Return
This is the time it takes, from execution of RET(93), to return to the
processing that was interrupted.
5
m
s
Summary of Contents for CS1W-HCA12-V1
Page 2: ......
Page 6: ...vi...
Page 20: ...xx Conformance to EC Directives 7...
Page 38: ...18 Models and System Configurations Section 1 2...
Page 78: ...58 Fail safe Circuits Section 3 5...
Page 138: ...118 AR Area Section 6 4...
Page 204: ...184 Improved Instructions Section 7 14...
Page 222: ...202 Cycle Time Section 8 3...
Page 240: ...220 Troubleshooting Flowcharts Section 9 5...
Page 244: ...224 Precautions when Using the CX Programmer Appendix A...
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Page 253: ......
