pciGrabber-4x4
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PHYTEC Messtechnik GmbH 2008 L-720e_0
6.1.4
Data storage by DMA and RISC-Program
This section describes the transfer of the data to the main memory and
the storage of the pixels to the addresses specified by the user.
As mentioned before, the transfer of the data is accomplished via two
DMA-channels, one for the odd and one for the even field. During the
time of digitization the DMA-controller of the pciGrabber-4x4 is con-
trolling the PCI-Bus and is
master
. The data are transferred in real
time along the PCI-bus to the main memory. This is possible because
of the high transfer rate of the PCI-bus.
The picture data are sent in real-time over the PCI bus to the PCI
Express-to-PCI-Bridge. From there the data are sent over the PCI
Express bus and will transmit into the main memory. This is possible
by the high transmission speed of the PCI and PCI Express bus.
Delays of the data transfer or for time intervals the PCI-bus is not
available to the Grabber (that means some other devices become
master), are bypassed by a FIFO-memory. This allows only a short
time span to bypass the blocked bus, since otherwise an overflow
might occur and portions of the image are lost. The bus is controlled
by the parameter
Maximum_Latency
and
Minimum_Grant
of the
PCI-board. If required, this parameters have to be adapted to the data
transfer rate, to the system configuration and to the bus performance.
The pciGrabber-4x4 is very flexible concerning the storage of the
data. The user can specify destination and format of the data within a
certain scope. For this a mechanism is required to separate the
continuous flow of data into partitions and direct the data to the
required addresses.
This mechanism is accomplished by the pciGrabber-4x4 with the help
of the
pixel instruction list
. This is a RISC-program, which drives the
DMA-controller correspondingly.
This RISC-program has to be written by the user and must fulfill the
required tasks and has to match the data and image format. So the
