PulseBlasterDDS
III. Programming the PulseBlasterDDS
Instruction Set Architecture
Machine-Word Definition
The PulseBlaster pulse timing and control processor implements an 80-bit wide Very Long
Instruction Word (VLIW) architecture. The VLIW memory words have specific bits/fields dedicated to
specific purposes, and every word should be viewed as a single instruction of the micro-controller.
The maximum number of instructions that can be loaded to on-board memory is 32k. The execution
time of instructions can be varied and is under (self) control by one of the fields of the instruction word
– the shortest being five clock cycles (for 512 memory-word models) and the longest being 2^52 clock
cycles. All instructions have the same format and bit length, and all bit fields have to be filled. Figure
3 shows the fields and bit definitions of the 80-bit instruction word.
Bit Definitions for the 80-bit Instruction Word (VLIW)
Output/Control Word
| Data Field
| OP Code
| Delay Count
(24 bits) (20 bits) (4 bits) (32 bits)
Figure 3:
Bit definitions of the 80-bit instruction/memory word
Breakdown of 80-bit Instruction Word
The 80-bit VLIW is broken up into 4 sections
1. Output Pattern and Control Word - 24 bits
2. Data Field - 20 bits
3. OP Code - 4 bits
4. Delay Count - 32 bits
Output Pattern and Control Word
Please refer to Table 1, next page, for output pattern and control bit assignments of the 24-bit
output/control word.
9/20/200511
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