TOBY-L4 series - System Integration Manual
UBX-16024839 - R04
System description
Page 15 of 143
Function
Pin Name
Pin No
I/O
Description
Remarks
UART1
RXD1
160
O /
O
UART1 data output /
SPI1 MOSI
1.8 V output, Circuit 104 (RXD) in ITU-T V.24,
alternatively configurable as SPI1 MOSI by uCPU API.
See section 1.9.2 / 1.9.3 for functional description.
See section 2.6.2 / 2.6.3 for external circuit design-in.
TXD1
159
I /
I
UART1 data input /
SPI1 MISO
1.8 V input, Circuit 103 (TXD) in ITU-T V.24,
alternatively configurable as SPI1 MISO by uCPU API.
Internal pull-up to
V_INT
enabled when UART1 data input.
See section 1.9.2 / 1.9.3 for functional description.
See section 2.6.2 / 2.6.3 for external circuit design-in.
CTS1
195
O /
O
UART1 CTS output /
SPI1 Chip Select
1.8 V output, Circuit 106 (CTS) in ITU-T V.24,
alternatively configurable as SPI1 Chip Select by uCPU API.
See section 1.9.2 / 1.9.3 for functional description.
See section 2.6.2 / 2.6.3 for external circuit design-in.
RTS1
193
I /
O
UART1 RTS input /
SPI1 Clock
1.8 V input, Circuit 105 (RTS) in ITU-T V.24,
alternatively configurable as SPI1 Clock by uCPU API.
Internal pull-up to
V_INT
enabled when UART1 RTS input.
See section 1.9.2 / 1.9.3 for functional description.
See section 2.6.2 / 2.6.3 for external circuit design-in.
UART2
RXD2
162
O
UART2 data output
1.8 V output, Circuit 104 (RXD) in ITU-T V.24.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
TXD2
161
I
UART2 data input
1.8 V input, Circuit 103 (TXD) in ITU-T V.24.
Internal active pull-up to
V_INT
.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
UART3
RXD3
19
O
UART3 data output
1.8 V output, Circuit 104 (RXD) in ITU-T V.24.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
TXD3
18
I
UART3 data input
1.8 V input, Circuit 103 (TXD) in ITU-T V.24.
Internal active pull-up to
V_INT
.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
SPI0
SPI_MOSI
174
O
SPI0 Master Output
Slave Input
1.8 V, SPI0 data output.
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.
SPI_MISO
169
I
SPI0 Master Input
Slave Output
1.8 V, SPI0 data input.
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.
SPI_SCLK
179
O
SPI0 Shift Clock
1.8 V, SPI0 clock.
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.
SPI_CS
173
O
SPI0 Chip Select 0
1.8 V, SPI0 chip select 0.
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.
I2C0
SCL
54
O
I2C0 clock
1.8 V open drain.
External pull-up required.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
SDA
55
I/O
I2C0 data
1.8 V open drain.
External pull-up required.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
