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Series AVME9125                                                                                                     VMEbus 6U Analog Input Board
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Start Channel Value Register (Read/Write, 49H)

The Start Channel Value register can be written with a 5-bit

value to select the first channel that is to be converted once
conversions have been triggered.  All channels including and
between the start and end channel values are converted.  A single
channel can be selected by writing the desired channel value in
both the Start and End Channel Value registers.

The Start Channel Value register can be read or written with 8-

bit data transfers.  In addition, the Start Channel Value register
can be simultaneously accessed with the End Channel Value via a
16-bit data transfer.  The unused bits are zero when read.  The
register contents are cleared upon reset.

Start Channel Value Register

Unused

Start Channel Value

07     06     05

04

03

02

01

00

After a data conversion cycle, the internal hardware pointers

are reinitialized to the start channel value.  Thus, when
conversions are started again, the first channel converted is
defined by the Start Channel Value register.

End Channel Value Register (Read/Write, 48H)

The End Channel Value register can be written with a 5-bit

value to indicate the last channel in a sequence to be converted.
When scanning, all channels between and including the start and
end channels are converted.  A single channel can be selected by
writing the desired channel value in both the Start and End
Channel Value registers.

The End Channel Value register can be read or written with 8-

bit data transfers.  In addition, the End Channel Value register can
be simultaneously accessed with the Start Channel Value with a
16-bit data transfer.  The unused data bits are zero when read.
The register contents are cleared upon reset.

End Channel Value Register

Unused

End Channel Value

15     14     13

12

11

10

09

08

New Data Registers (Read Only, 4AH to 4DH)

The New Data registers can be read to determine which

channels of the Mail Box buffer contain new converted data.  A set
bit in the New Data register indicates that the Mail Box buffer,
corresponding to the channel of the set bit, contains new
converted data.  A set New Data register bit is cleared upon a read
of its corresponding Mail Box buffer.

The New Data bits are also cleared at the start of all new data

acquisition cycles initiated with the Software Start Convert
command.  This is done to avoid mistaking data from an old scan
cycle with that of a new scan cycle.

The New Data registers can be read via 16-bit or 8-bit data

transfers.  In addition, the register contents are cleared upon reset.

New Data Register (Read Only, 4BH)

Data  Bit

07

06

05

04

03

02

01

00

Channel

07

06

05

04

03

02

01

00

New Data Register (Read Only 4AH)

Data  Bit

15

14

13

12

11

10

09

08

Channel

15

14

13

12

11

10

09

08

New Data Register (Read Only 4DH)

Data  Bit

07

06

05

04

03

02

01

00

Channel

23

22

21

20

19

18

17

16

New Data Register (Read Only 4CH)

Data  Bit

15

14

13

12

11

10

09

08

Channel

31

30

29

28

27

26

25

24

Missed Data Registers (Read Only, 4EH to 51H)

The Missed Data registers can be read to determine if a

channel’s Mail Box buffer has been overwritten with new converted
data before the last converted value was read.  A set bit in the
Missed Data register indicates a converted value corresponding to
the channel of the set bit was overwritten before being read.  A set
Missed Data register bit is cleared upon a read of its
corresponding Mail Box buffer.

The Missed Data bits are also cleared at the start of all new

data acquisition cycles initiated with the Software Start Convert
command.  This is done to avoid mistaking missed data from an
old scan cycle with that of a new scan cycle.

The Missed Data registers can be read via 16-bit or 8-bit data

transfers.  In addition, the register contents are cleared upon reset.

Missed Data Register (Read Only, 4FH)

Data  Bit

07

06

05

04

03

02

01

00

Channel

07

06

05

04

03

02

01

00

Missed Data Register (Read Only 4E)

Data  Bit

15

14

13

12

11

10

09

08

Channel

15

14

13

12

11

10

09

08

Missed Data Register (Read Only 51H)

Data  Bit

07

06

05

04

03

02

01

00

Channel

23

22

21

20

19

18

17

16

Missed Data Register (Read Only 50H)

Data  Bit

15

14

13

12

11

10

09

08

Channel

31

30

29

28

27

26

25

24

Start Convert Register (Write Only, 52H)

The Start Convert register is a write-only register and is used

to trigger conversions by setting data bit-0 of this register to a logic
one.  The desired mode of data acquisition must first be
configured by setting the following registers to the desired values
and modes: Control, Timer Prescaler, Conversion Timer, Start
Channel Value, End Channel Value, and Interrupt Vector.

This register can be written with either a 16-bit or 8-bit data

value.  Data bit-0 must be a logic one to initiate data conversions.

Start Convert Register

Not Used

Start Convert

D15 to D01

D00

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Summary of Contents for AVME9125 Series

Page 1: ...ess underutilized and idle equipment along with credit for buybacks and trade ins Custom engineering so your equipment works exactly as you specify Critical and expedited services Leasing Rentals Demo...

Page 2: ...South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 624 1541 Fax 248 624 9234 Copyright 1998 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500...

Page 3: ...CONTROL LOGIC 15 ANALOG INPUTS 15 Power Supply Filters 15 5 0 SERVICE AND REPAIR 15 SERVICE AND REPAIR ASSISTANCE 15 PRELIMINARY SERVICE PROCEDURE 16 6 0 SPECIFICATIONS 16 PHSICAL 16 VMEbus COMPLIANC...

Page 4: ...or upon completion of conversion of the group of all scanned channels Software Programmable Interrupt Level The VMEbus interrupt level is software programmable Additional registers are associated wit...

Page 5: ...rs for different base address locations is shown in Table 2 1 IN means that the pins are shorted together with a shorting clip OUT indicates that the clip has been removed The jumper locations are sho...

Page 6: ...ME9125 The EXP9125 will pull CHSel0 high when present Lastly the AVME9125 provides 15 volts to the EXP9125 via the P2 connector Pin assignments for the P2 connectors of the AVME9125 are shown in Table...

Page 7: ...Identification Space Not Used Card Identification Space Low Byte 01 3F 40 Status Register 41 42 Control Register 43 44 Timer Prescaler Interrupt Vector Register 45 46 Conversion Timer 47 48 End Channe...

Page 8: ...is set to 0 Reset condition Set to 0 Bit 0 EXP9125 Board Present Status Read This bit will be 1 when the EXP9125 Expander board is present in a slot adjacent to the AVME9125 A set bit indicates that 3...

Page 9: ...gister The resulting frequency can be used to generate periodic triggers for precisely timed intervals between conversions The Timer Prescaler has a minimum allowed value restriction of 5A hex or 90 d...

Page 10: ...tiated with the Software Start Convert command This is done to avoid mistaking data from an old scan cycle with that of a new scan cycle The New Data registers can be read via 16 bit or 8 bit data tra...

Page 11: ...e an offset of 10 Bit D2 can not be set since an offset of 9 would result and 9 is greater then 9 25 Finally bits D1 and D0 are also set The value written to the offset coefficient must be 3DB hex as...

Page 12: ...econds after the programmed interval has lapsed If interrupt upon completion of a group of channels is selected an interrupt will be issued 10 5 seconds after the interval time of the last selected ch...

Page 13: ...tal Signal Processing logic for real time calibration of digitized values The on board hardware implements the required multiplication to adjust the gain and also the summation to correct the offset T...

Page 14: ...Corresponding Registers 13 Since all parameters are known the gain and offset coefficients can be determined A The offset coefficient is the average of the 32 Count0V values measured An example illus...

Page 15: ...cally 800ns for accesses to the AVME9125 board registers The board s FPGA monitors the base address jumper setting which is jumperable on 256 byte boundaries in the VMEbus Short I O A16 Address Space...

Page 16: ...o Table 2 3 Field I O signals are NON ISOLATED This means that the field return and logic common have a direct electrical connection to each other As such care must be taken to avoid ground loops see...

Page 17: ...al 600mA Maximum VMEbus COMPLIANCE Specification This device meets or exceeds all written VME specifications per revision C 1 dated October 1985 IEC 821 1987 and IEEE 1014 1987 Data Transfer Bus A16 D...

Page 18: ...the uniform single sample mode A 3 foot shielded analog input ribbon was used ENVIRONMENTAL Operating Temperature 0 to 70 C Relative Humidity 5 95 non condensing The printed circuit board is coated w...

Page 19: ...VMEbus 6U Analog Input Board ___________________________________________________________________________________________ 18 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE ww...

Page 20: ...VMEbus 6U Analog Input Board ___________________________________________________________________________________________ 19 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE ww...

Page 21: ...SHIELDED CABLE IS RECOMMENDED FOR LOWEST NOISE SHIELD IS CONNECTED TO GROUND REFERENCE AT ONE END ONLY TO PROVIDE SHIELDING WITHOUT GROUND LOOPS NOTES CH16 31 EXT SOURCE 16 31 SEE NOTE 2 SEE NOTE 1 SH...

Page 22: ...uipment Have surplus equipment taking up shelf space We ll give it a new home Learn more Visit us at artisantg com for more info on price quotes drivers technical specifications manuals and documentat...

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